Data structures, methods and primitive block generators for storing primitives in a graphics processing system. The method includes: receiving a primitive associated with state data that defines how the primitive is to be rendered; determining whether the state data associated with the received primitive matches state data for a current primitive block; and in response to determining that the state data for the received primitive matches the state data for the current primitive block: determining, based on one or more primitive section size constraints, whether the received primitive is to be added to a current primitive section of the current primitive block in a data store; in response to determining that the received primitive is to be added to the current primitive section, adding the received primitive to the current primitive section; and in response to determining that the received primitive is not to be added to the current primitive section: outputting the current primitive section; reconfiguring the data store to store a new primitive section for the current primitive block; and adding the received primitive to the new primitive section for the current primitive block.

A central processing unit executes a graphics accelerated operation during a pre-boot basic input/output system (BIOS). The central processing unit initializes multiple protocol scheduler circuitry during an early phase of the pre-boot BIOS. The multiple protocol scheduler circuitry initializes host memory pages, and creates one or more bit block transfer tasklets during the pre-boot BIOS. A graphics processing core executes one of the bit block transfer tasklets, and renders a graphical user interface element for display during the pre-boot BIOS.

In one embodiment, a computing system may write a first set of pixel values in a tile order into a first buffer with the pixel values organized into a first set of tiles. The system may generate first validity data for the first set of tiles. The first validity data may include a validity indicator for each tile to indicate if that tile is a valid tile. The system may read from the first buffer a first subset of pixel values in a pixel row order corresponding to pixel rows of the first set of tiles based on the valid data. The first subset of pixel values may be associated with valid tiles of the first set of tiles. The system may send the first subset of pixel values and the first validity data of the first set of tiles to a display via an output data bus.

A display system may include a memory external to a pixel that stores a first digital data value, a memory internal to the pixel that stores a second digital data signal, where a combination of the first digital data signal and the second digital data signal may indicate a target gray level assigned to the pixel for a particular image frame. The pixel may be driven for a first duration of time according to the first digital data signal and for a second duration of time according to the second digital data signal.

A system is disclosed for processing and streaming real-time graphics by a video-server for synchronized output via secondary-network connected display adapters to multiple displays arranged as a video-wall. This system enables the video-server to leverage performance advantages afforded by advanced GPUs, combined with low-cost Smart displays or System-on-Chip devices to deliver advanced realtime video-wall capabilities over the network while offering flexibility in the selection of network display adapters and still achieving synchronized output of multiple sub-image streams to selected end-point displays. This has applications generally in the field of real-time multiple-display graphics distribution as well as specific applications in the field of network video-walls. A method and computer readable medium are also disclosed that operate in accordance with the system.

The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.

A method and system of transmitting a plurality of area-of-interest video codestreams is described. A first video codestream and one or more second video codestreams are generated from a plurality of large format images that are captured. The first video codestream has a first plurality of areas-of-interest selected from the plurality of large format images and the one or more second video codestream have at least a second plurality of areas-of-interest from the same plurality of large format images. The first video codestream is generated at a first frame rate and each of the second video codestreams is generated at a second frame rate. The first and second video codestreams are combined to obtain a combined video codestream. The combined video codestream is then transmitted to a computer system that regenerates the first video codestream and the one or more second video codestreams at their respective frame rates.

An apparatus and method are described for allocating local memories to virtual machines. For example, one embodiment of an apparatus comprises: a command streamer to queue commands from a plurality of virtual machines (VMs) or applications, the commands to be distributed from the command streamer and executed by graphics processing resources of a graphics processing unit (GPU); a tile cache to store graphics data associated with the plurality of VMs or applications as the commands are executed by the graphics processing resources; and tile cache allocation hardware logic to allocate a first portion of the tile cache to a first VM or application and a second portion of the tile cache to a second VM or application; the tile cache allocation hardware logic to further allocate a first region in system memory to store spill-over data when the first portion of the tile cache and/or the second portion of the file cache becomes full.

Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.

With respect to a space including an object 40 of a display target, images of the space viewed from reference points 42a to 42c of view are created as reference images 46a, 46b, and 46c in advance and they are synthesized according to a position of an actual point of view to render a display image. In the certain reference image 46b, data other than a part 48 represented only in it is deleted. At the time of rendering of the deleted part, the other reference images 46a and 46c are used.