A video processing device processing input videos, includes a video processing unit that processes the input videos; and a control unit that sets a control value for controlling the video processing unit, wherein an entire input video is constituted by combining the input videos, and among partial areas associated with the respective input videos constituting the entire input video, one of the partial areas is defined as a first partial area, and another of the partial areas adjacent to, the first partial area is defined as a second partial area, and when processing which is performed, by referring to a pixel value in one of the first partial area and the second partial area, on another of the first partial area and the second partial area, is defined as adjacent boundary processing, the video processing unit performs the adjacent boundary processing on the entire input video, and generates processed videos.

A configuration of an image processing apparatus is simplified. In a display apparatus, a first sub input image and a second sub input image are input to a first back-end processor, and a first residual input image and a second residual input image are input to a second back-end processor. A first entire input image is constituted by combining the first sub input image and the first input image. In a case where the display apparatus processes the first entire input image, the first back-end processor processes the first sub input image, and the second back-end processor processes the first residual input image.

A memory management system for generating 3-dimensional computer images is provided. The memory management system includes a device for subdividing an image into a plurality of rectangular areas, a memory for storing object data pertaining to objects in the image which fall in each rectangular area, a device for storing the object data in the memory, a device for deriving image data and shading data for each rectangular area from the object data, a device for supplying object data for each rectangular area from the respective portion of the memory and, if the rectangular area contains objects also falling in at least one other rectangular area, also from the global list, to the deriving device, and a device for storing the image data and shading data derived by the deriving device for display. The memory includes at least one portion allocated to each rectangular area and at least one portion allocated as a global list.

Example techniques are described for generating graphics content by assigning a first region of the graphics content to a first tile, assigning a second region of the graphics content to a second tile, determining, at the first tile and at a first resolution, a first set of samples of the graphics content for each pixel of multiple pixels associated with the first region, determining, at the second tile and at a second resolution that is lower than the first resolution, a second set of samples of the graphics content for each pixel of multiple pixels associated with the second region, downsampling the first set of samples into a combined set of samples, preserving samples of the second set of samples to generate a third set of samples with preserved samples, storing the combined set of samples, and storing the third set of samples with preserved samples.

There is disclosed in one example a video processor, including: an input buffer to receive an input image; a slicer circuit to divide the input image into a plurality of N vertical slices; N parallel input buffers for de-rasterization; N parallel image scalers, wherein each scaler is hardware configured to scale in a raster form, one of the N vertical slices according to an image scaling algorithm; N parallel output buffers for rerasteriztion; and an output multiplexer to combine the scaled vertical slices into a combined scaled output image.

Embodiments of the present disclosure efficiently create a single video stream from a plurality of individual video streams. The single video stream may embody a grid-based presentation of the individual video streams, without requiring separate objects for each stream. Such embodiments utilize particular hardware-accelerated multiplexing image pipelines executed via one or more graphics processing unit for efficient processing. Embodiments include a multiplexer component configured to perform the hardware-accelerated image pipelines executed on one or more GPUs. Some such embodiments output a common output video that may be outputted for a variety of use cases, including but without limitation outputting to a display wall, outputting to one or more web-based client devices, outputting locally to a client device, and outputting locally to a multimonitor display. Some embodiments generate utilize an image primitive frame that is sharable between multiplexers for use in different use cases without need to repeat processing steps.

Conservative rasterization hardware comprises hardware logic arranged to perform an edge test calculation for each edge of a primitive and for two corners of each pixel in a microtile. The two corners that are used are selected based on the gradient of the edge and the edge test result for one corner is the inner coverage result and the edge test result for the other corner is the outer coverage result for the pixel. An overall outer coverage result for the pixel and the primitive is calculated by combining the outer coverage results for the pixel and each of the edges of the primitive in an AND gate. The overall inner coverage result for the pixel is calculated in a similar manner.

Conservative rasterization hardware comprises hardware logic arranged to perform an edge test calculation for each edge of a primitive and for two corners of each pixel in a microtile. The two corners that are used are selected based on the gradient of the edge and the edge test result for one corner is the inner coverage result and the edge test result for the other corner is the outer coverage result for the pixel. An overall outer coverage result for the pixel and the primitive is calculated by combining the outer coverage results for the pixel and each of the edges of the primitive in an AND gate. The overall inner coverage result for the pixel is calculated in a similar manner.

In one embodiment, a computing system may write a first set of pixel values in a tile order into a first buffer with the pixel values organized into a first set of tiles. The system may generate first validity data for the first set of tiles. The first validity data may include a validity indicator for each tile to indicate if that tile is a valid tile. The system may read from the first buffer a first subset of pixel values in a pixel row order corresponding to pixel rows of the first set of tiles based on the valid data. The first subset of pixel values may be associated with valid tiles of the first set of tiles. The system may send the first subset of pixel values and the first validity data of the first set of tiles to a display via an output data bus.

Systems, apparatuses, and methods for implementing a single-stream foveal display transport are disclosed. A system includes a transmitter sending an image over a display transport as a sequence of equi-sized rectangles to a receiver coupled to a display. The receiver then scales up the rectangles with different scale factors to cover display areas of different sizes. The pixel density within a rectangular region is uniform and scaling factors can take on integer or non-integer values. The rectilinear grid arrangement of the image results in simplified scaling operations for the display. In another scenario, the image is transmitted as a set of horizontal bands of equal size. Within each band, the same horizontal amount of transmitted pixels are redistributed across multiple rectangular regions of varied scales. The display stream includes embedded information and the horizontal and/or vertical distribution and scaling of rectangular regions, which can be adjusted for each transmitted image.