A video processing device processing input videos, includes a video processing unit that processes the input videos; and a control unit that sets a control value for controlling the video processing unit, wherein an entire input video is constituted by combining the input videos, and among partial areas associated with the respective input videos constituting the entire input video, one of the partial areas is defined as a first partial area, and another of the partial areas adjacent to, the first partial area is defined as a second partial area, and when processing which is performed, by referring to a pixel value in one of the first partial area and the second partial area, on another of the first partial area and the second partial area, is defined as adjacent boundary processing, the video processing unit performs the adjacent boundary processing on the entire input video, and generates processed videos.

An image signal processor for generating a converted image based on a raw image includes processing circuitry configured to store data corresponding to a plurality of lines of a received image in a line buffer, perform an image processing operation by filtering the data stored in the line buffer based on at least one filter, and divide the raw image into a plurality of sub-images and request the plurality of sub-images from a memory in which the raw image is stored, such that the plurality of sub-images are sequentially received by the line buffer, a width of each of the plurality of sub-images being less than a width of the line buffer, and the plurality of sub-images being parallel to each other.

The present disclosure relates to methods and apparatus for graphics processing. An example method generally includes receiving, at a graphics processing unit (GPU), a plurality of commands corresponding to a plurality of draws across a frame, each of the plurality of commands indicating a depth test direction with respect to a low-resolution depth (LRZ) buffer for the corresponding draw. The method generally includes maintaining, at the GPU, a LRZ status buffer to store a corresponding depth test direction for a first command in time of the plurality of commands processed by the GPU. The method generally includes disabling, at the GPU, use of the LRZ buffer for depth testing for any of the plurality of commands remaining unprocessed after processing a command of the plurality of commands having a different depth test direction than the corresponding depth test direction stored in the LRZ status buffer.

A disclosed technique includes prefetching display data into a cache memory, wherein the display data includes data to be displayed on a display during a memory black-out period for a memory; triggering the memory black-out period; and during the black-out period, reading from the cache memory to obtain data to be displayed on the display.

An apparatus to facilitate memory tiling is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads via access to the memory and tiling logic to apply a tiling pattern to memory addresses for data stored in the memory.

A system for updating an image on a display device includes pixels in a pixel array. The system includes a display subsystem for executing commands and displaying images, the display subsystem also includes a parser for receiving image frame data, and extracting updated image data and commands. A storage device is used for storing the updated image data in an updated cache location according to the commands. A loader is used for reading the commands to identify and fetch the updated image data from the storage device. Display backplane circuitry is used for receiving the updated image data from the loader and for updating pixel driver circuity for pixels within the updated image data. The examples described are ideal for driving micro-displays such as LCoS micro-LED displays.

The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may process at least one frame including frame content associated with a grid including a plurality of grid sections, each of a plurality of portions of the frame content being aligned with at least a portion of at least one of the plurality of grid sections. The apparatus may also shift the frame content with respect to the grid, such that at least one portion of the plurality of portions of the frame content is aligned with at least a portion of at least one distinct grid section of the plurality of grid sections. Additionally, the apparatus may store the shifted frame content including the at least one portion of the frame content that is aligned with at least a portion of the at least one distinct grid section.

The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.

The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.

Embodiments of this application disclose a VR display control method, an electronic device, and a computer-readable storage medium. In embodiments of this application, a VR desktop may be generated, so that the VR desktop is displayed on a virtual reality display device. In addition, an operation performed by a user on a first application icon on the VR desktop is received, where the first application icon is associated with a first application installed on the electronic device. Therefore, content of the first application may be displayed through the virtual reality display device, where the content of the first application is displayed on a curved surface screen that is obtained through conversion from a rectangular screen. In embodiments of this application, a most eye-friendly curvature effect may be achieved through a VR virtual scene, so that visual experience of the user can be enhanced, and user experience can be improved.