Aspects of the disclosure provide a method and device for storing an input image into a memory. The disclosure describes allocating one or more frame buffers in the memory. The disclosure further describes dividing the input image into access units corresponding to subsets of the input image and allocating a main portion and a secondary portion in the frame buffer for each of the access units, wherein at least one of the secondary portions is not sequentially located after its respective main portion within the frame buffer. The disclosure also describes compressing the access units into compressed access units and storing each of the compressed access units into its respective main portion, and if a size of the compressed access unit exceeds a size of the main portion, then storing a remainder of the compressed access unit into its respective secondary portion.

Aspects of the disclosure provide a method for merging compressed access units according to compression rates and/or positions of the respective compressed access units. The method can include receiving a sequence of compressed access units corresponding to a sequence of raw access units partitioned from an image or a video frame and corresponding to a sequence of memory spaces in a frame buffer, determining a merged access unit including at least two consecutive compressed access units based on compression rates and/or positions of the sequence of compressed access units. The merged access unit is to be stored in the frame buffer with a reduced gap between the at least two consecutive compressed access units compared with storing the at least two consecutive compressed access units in corresponding memory spaces in the sequence of memory spaces.

A system, includes a controller configured to obtain, for an image frame stored in a frame memory image, data associated with a color component and generate dithered bit planes having a dither noise pattern, the dithered bit planes including time repeated bit plane sequences in the image frame. The system also includes a spatial light modulator (SLM) coupled to the controller. The SLM is configured to project an image of the image frame according to the dithered bit planes. Additionally, the system includes a light source optically coupled to the SLM. The light source is configured to provide light for projecting the image.

A data processing method and device for a Light emitting diode (LED) Television (TV), and an LED TV are disclosed, the data processing device includes: a signal processing chip configured to perform mode conversion on a received TV signal so as to obtain a first video signal of a preset mode; and a video processing chip connected to the signal processing chip and configured to perform clock synchronization processing on the first video signal so as to obtain a second video signal and output the second video signal to an LED display. The problem in the prior art that an LED TV can only display a TV signal of a single mode is solved, thereby achieving the effect that the LED TV can display videos of various modes and various formats.

A pixel circuit includes a capacitor, a light emitting control transistors, a driving transistor, and multiple light emitting transistors. The light emitting control transistor includes a gate electrode coupled to a light emitting control signal, a source electrode coupled to a supply voltage, and a drain electrode. The driving transistor includes a gate electrode coupled to the capacitor, a source electrode coupled to the drain electrode of the light emitting control transistor, and a drain electrode. Each light emitting transistor includes a gate electrode coupled to a respective light emitting signal, a source electrode coupled to the drain electrode of the driving transistor, and a drain electrode coupled to a respective light emitting element. Each light emitting signal turns on the respective light emitting transistor during a respective light emitting period within a frame period to cause the respective light emitting element to emit a light. The light emitting control signal turns on the light emitting control transistor during each light emitting period within the frame period.

An electronic paper display apparatus including an electronic paper display panel to display an image page, a display driver coupled to the electronic paper display panel, and a data processor coupled to the display driver. The display driver drives the electronic paper display panel to display a plurality of image frames according to image data, so as to display the image page. The data processor converts a first look-up table into a second look-up table and merges a current frame and a previous frame into a combined frame. The data processor generates the image data according to the combined frame and the second look-up table and outputs the image data. The image frames include the current frame and the previous frame. A driving method of the electronic paper display apparatus is also provided.

One embodiment of the present invention sets forth a technique for converting alpha values into pixel coverage masks. Geometric coverage is sampled at a number of real sample positions within each pixel. Color and depth values are computed for each of these real samples. Fragment alpha values are used to determine an alpha coverage mask for the real samples and additional virtual samples, in which the number of bits set in the mask bits is proportional to the alpha value. An alpha-to-coverage mode uses the virtual samples to increase the number of transparency levels for each pixel compared with using only real samples. The alpha-to-coverage mode may be used in conjunction with virtual coverage anti-aliasing to provide higher-quality transparency for rendering anti-aliased images.

System address reconstruction logic in accordance with one embodiment of the present description, reconstructs a system address from a channel address translated from the system address. The system address reconstruction logic includes logic configured to reconstruct one or more systems address fields as a function of the channel address, the number of memory controller target ways of the memory being equal to three, the number of bits of the granularity of interleaving of data among the memory controller target ways, the number of channels per memory controller target way, and the number of bits of the granularity of interleaving of data among the channels of a memory controller target way. Other aspects are described herein.

According to one embodiment, a display device includes a plurality of pixels each including a plurality of subpixels, each subpixel including a luminescent element, a plurality of scanning lines, a plurality of image signal lines, a plurality of reset power source lines, a first power source line, a scanning line driving circuit and a signal line driving circuit, wherein at least one subpixel comprises an output switch, a driving transistor, a retaining capacitance, a pixel switch and a reset switch, and the output switch is shared with a plurality of subpixels included in at least one pixel.

The disclosure discloses a data processing method and device for a Light emitting diode (LED) Television (TV), and an LED TV, wherein the data processing device includes: a signal processing chip configured to perform mode conversion on a received TV signal so as to obtain a first video signal of a preset mode; and a video processing chip connected to the signal processing chip and configured to perform clock synchronization processing on the first video signal so as to obtain a second video signal and output the second video signal to an LED display. By means of the disclosure, the problem in the prior art that an LED TV can only display a TV signal of a single mode is solved, thereby achieving the effect that the LED TV can display videos of various modes and various formats.