The present invention includes a write-in start position control section (36) that performs a process of shifting, by a given shifting amount, a start position of a write-in operation to the frame memory (31), when the write-in operation is started, the given shifting amount being predetermined so as not to exceed a capacity reserved in advance in the frame memory.

A single chip set-top box system and method is provided. The system comprises, for example, a transceiver, an audio/video decoder, a CPU, peripherals, DAVIC MAC and a graphics processor. The transceiver receives a digitally modulated compressed audio/video signal, and the audio/video decoder receives the compressed audio/video signal from the transceiver and decompresses the compressed audio/video signal. The graphics processor blends the decompressed audio/video signal with graphics to generate a blended video image with audio.

A system comprises storage that includes a shell application and a sub-application that is adapted to provide a functionality to the shell application. The system also comprises processing logic coupled to the storage and adapted to execute the shell application and the sub-application. The processing logic generates a first graphical user interface (GUI) using the sub-application and generates a second GUI using the shell application. The processing logic displays on a display the first GUI superimposed onto the second GUI. The processing logic captures input provided using the first GUI and provides the input to the sub-application.

One embodiment of the present invention discloses a method for processing video data within a video data processing path of a processing unit. The video data processing path includes three stages. In the first stage, source operands are extracted from a local register file and are ordered to map efficiently onto the downstream data path. In the second stage, arithmetic operations are performed on the source operands based on video processing instructions to generate intermediate results. In the third stage, additional operations are performed on the intermediate results based on the video processing instructions. In some embodiment, the intermediate results are combined with additional operands retrieved from the local register file.

An information handling system includes a processor; a memory, a firmware, and a video agent. The memory includes a frame buffer for image data. The frame buffer accessible to an operating system. The firmware is configured to present to the operating system a graphics output protocol. The graphics output protocol includes an address of the portion of the reserved portion of the memory and soft video display parameters. The video agent is configured to retrieve image data from the reserved portion of the memory, and provide the image data to an external system for remote video display to be completed upon finalization of application.

Technologies for low-power display refresh standby include a computing device with a display such as an LCD panel. The computing device may include a system-on-a-chip (SoC) with a processor, I/O subsystem, display controller, and memory. When the computing device determines that a display image is static, the computing device enters a low-power display refresh standby mode, powering down unneeded components of the SoC such as processor cores, peripheral devices, and memory other than a dedicated display buffer. The display controller may access the dedicated display buffer via the I/O subsystem and output the image to the display. The computing device may power down the I/O subsystem and the dedicated display buffer when a display controller FIFO is full of image data, and periodically power on the I/O subsystem and display buffer to fill the display controller FIFO. Other embodiments are described and claimed.

A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.

Circuitry for adjusting luminance of a display device is provided. The circuitry includes a non-volatile memory array having a plurality memory cells configured to store luminance data of the display device, and a luminance adjusting circuit configured to receive image data to be displayed on the display device. The luminance adjusting circuit is coupled directly to the non-volatile memory array to receive the luminance data of the display device from the non-volatile memory array and adjust the image data based on the luminance data of the display device.

An apparatus and method are described for allocating local memories to virtual machines. For example, one embodiment of an apparatus comprises: a command streamer to queue commands from a plurality of virtual machines (VMs) or applications, the commands to be distributed from the command streamer and executed by graphics processing resources of a graphics processing unit (GPU); a tile cache to store graphics data associated with the plurality of VMs or applications as the commands are executed by the graphics processing resources; and tile cache allocation hardware logic to allocate a first portion of the tile cache to a first VM or application and a second portion of the tile cache to a second VM or application; the tile cache allocation hardware logic to further allocate a first region in system memory to store spill-over data when the first portion of the tile cache and/or the second portion of the file cache becomes full.