Technologies are generally described for implementing an information rendering scheme. In some examples, a method performed under control of an end device may include obtaining a decryption key; decrypting encrypted information based on the obtained decryption key; and rendering the decrypted information stored in a video random access memory (VRAM) that is operatively connected to a graphic processing unit (GPU) of the end device.

A signal processing circuit, complying with DisplayPort standard and operated in a display device which is as a DisplayPort sink device, includes a main physical circuit, which is configured to receive a first signal from one of a plurality of DisplayPort connectors of the display device connected to a first DisplayPort source device and a plurality of auxiliary physical circuits. Only a first auxiliary physical circuit of the plurality of auxiliary physical circuits is enabled to receive a second signal from the DisplayPort connector connected to the first DisplayPort source device.

The display controller (1) includes: a DRAM (31); a SRAM (32) which consumes electric power less than the DRAM (31); an update judging section (61); a secondary compression section (70); and a decompression section (40). In a case where the update judging section (61) has judged that image data is not updated, (i) the secondary compression section (70) compresses image data and then stores compressed image data in the SRAM (32), (ii) the DRAM (31) stops a memory retaining operation, and (iii) the decompression section (40) decompresses the compressed image data and then supplies decompressed data to an LCD (3).

The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.

A data processing method and device for a Light emitting diode (LED) Television (TV), and an LED TV are disclosed, the data processing device includes: a signal processing chip configured to perform mode conversion on a received TV signal so as to obtain a first video signal of a preset mode; and a video processing chip connected to the signal processing chip and configured to perform clock synchronization processing on the first video signal so as to obtain a second video signal and output the second video signal to an LED display. The problem in the prior art that an LED TV can only display a TV signal of a single mode is solved, thereby achieving the effect that the LED TV can display videos of various modes and various formats.

A camera affixed to a device including a display has the display viewer within the camera field of view (FOV). The camera is employed to track the movement of the display viewer's eyes and/or face and/or head with respect to the camera and display. A relative motion is determined based on the camera viewer tracking data. Content frame position within the display screen area is compensated based on the relative motion and displayed on the screen for a better, less-irritating viewing experience.

A first sum is calculated which is a sum of light intensities of dispersed lights generated when a pixel light by a target pixel passes through an optical system, and a first light intensity is calculated by adding the first sum to a light intensity of the pixel light of the target pixel. A second sum is calculated which is a sum, at a position of the target pixel, of each of light intensities of dispersed lights generated when each of pixel lights by pixels around the target pixel pass through the optical system. A second light intensity of the pixel light by the target pixel is calculated by subtracting the second sum from the first light intensity.

One device generates a first screen by executing some processes including a first process of rendering processing of the screen to be displayed in accordance with the information required to determine the rendered contents. On the other hand, devices except for the one device generates a second screen by executing some processes, which do not include the first process but include a second process different from the first process, of the rendering processing of the screen to be displayed in accordance with that information, and sends the second screen to the one device. Then, the one device receives the second screens generated by the respective devices except for the one device, and generates the screen to be displayed by compositing the first and second screens.

A camera affixed to a device including a display has the display viewer within the camera field of view (FOV). The camera is employed to track the movement of the display viewer's eyes and/or face and/or head with respect to the camera and display. A relative motion is determined based on the camera viewer tracking data. Content frame position within the display screen area is compensated based on the relative motion and displayed on the screen for a better, less-irritating viewing experience.

A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.