A display driver circuit receives externally-encoded image data and processes the data using a memory (graphic RAM), an internal encoder, and an external decoder configured to operate on the externally-encoded image data. The processed data is provided to a display device by a source driver of the display driver circuit. Data is processed through the graphic RAM and an internal decoder or the external decoder depending on whether a slice of the data is a currently received update slice, a recently received standby slice, or a still slice.

The present teaching relates to method, system, medium, and implementations for LED display. A first signal is received that signals a timing for a next data transfer. In response to the first signal, a bit-based image block stored in a memory is transferred, via a bus connected thereto, to one of a pair of alternate buffers pointed to by a write buffer pointer, which is subsequently toggled to point to another of the pair of alternate buffers. A second signal is received that signals a timing for refreshing the LED display. In response to the second signal, the bit-based image block is retrieved from the one of the pair of alternate buffers pointed to by a read buffer pointer, which is then toggled to point to the other of the pair of alternate buffers. The lights of the LED display are then refreshed in accordance with control signals generated based on the bit-based image block.

The present teaching relates to method, system, medium, and implementations for data transfer in LED display. A signal signaling a timing for a next data transfer is received. In response to the signal, a next data transfer instruction is obtained that instructs reading a bit-based image block of an image from a memory. The bit-based image block is transferred, according to the next data transfer instruction, from the memory via a bus connected thereto, to one of a pair of alternate buffers pointed to by a write buffer pointer. Then, the write buffer pointer is toggled to point to another of the pair of alternate buffers and the process repeats. The bit-based image blocks alternately stored in the buffers are later retrieved and displayed on the LED display.

Systems and methods are configured to adjust the timing of rendered frame scanout in response to fluctuations in a variable frame rate at which source frames are rendered.

An image display system includes at least one user parameter analyser configured to determine at least one parameter associated with a user, an image display screen having luminous pixels, at least one graphics processing unit configured to process at least one first main image that can be displayed on the image display screen and that is representative of a first zone of a main scene. The system further includes at least one image buffer device configured to store at least the first main image, and a graphics controller configured to control a display of at least one first secondary image on the image display screen, the first secondary image having a first portion of the first main image included in the first main image and positioned within the first main image as a function of a first user parameter.

A system includes a display subsystem. The display subsystem includes a shared buffer having allocated portions, each allocated to one of a plurality of display threads, each display thread associated with a display peripheral. The display subsystem also includes a direct memory access (DMA) engine configured to receive a request from a main processor to deallocate an amount of space from a first allocated portion associated with a first display thread. In response to receiving the request, the DMA engine deallocates the amount of space from the first allocated portion and shifts the allocated portions of at least some of other display threads to maintain contiguity of the allocated portions and concatenate free space at an end of the shared buffer.

Systems and methods are configured to adjust the timing of source frame compression in response to fluctuations in a variable frame rate at which source frames are rendered.

An image display system includes a display device, a second memory circuit, and an image processor circuit. The display device includes a panel and a first memory circuit, in which the first memory circuit is configured to store first predetermined data for controlling the panel. The second memory circuit is configured to store second predetermined data. The image processor circuit is configured to read first part data in the first predetermined data and second part data in the second predetermined data and compare the first part data with the second part data. If the first part data is identical to the second part data, the image processor circuit is further configured to output a driving signal according to the second predetermined data to control the panel to start displaying an image

The present disclosure is directed to systems and methods of maintaining source device to sink device synchronization in systems in which the source device enters a Panel Self-Refresh (PSR/PSR2) mode and the sink device enables adaptive synchronization with the source device. To maintain synchronization, in some instances the source device and the sink device may maintain synchronization contemporaneous with at least a portion of the PSR/PSR2 operating mode. To maintain synchronization, in some instances, a high-bandwidth communications link may be maintained between the source device and the sink device. In some instances, synchronization between the source device and the sink device may be interrupted upon the source device entering the PSR/PSR2 operating mode and may be re-established upon the source device exiting the PSR/PSR2 operating mode.

Methods, systems, and devices for adaptive display data transfer rate to reduce power consumption during partial frame composition are described. The method may include identifying a set of frames for display on a panel of the device, determining a starting line of an updating frame region of the set of frames in relation to a first pixel line of the panel, determining an ending line of the updating frame region of the set of frames in relation to the first pixel line of the panel, reducing a bus bandwidth vote based on the starting line of the updating frame region, or the ending line of the updating frame region, or a number of lines of the updating frame region, or any combination thereof, and transferring the lines of the updating frame region from a display processor unit to a panel memory at the reduced bus bandwidth.