Techniques for selectively updating regions of a display are disclosed. In the illustrative embodiment, a display engine of a computing device sends messages to a display to update particular update regions of the display. As not the entire frame is sent, sending only the update regions can save bandwidth and power. In the illustrative embodiment, some of the update regions for a frame sent to the display may be compressed and some of the update regions for the frame may be uncompressed. Due to overhead in the compression, sending small update regions uncompressed may reduce the bandwidth and/or power used.

The present application discloses display apparatus for displaying image based on time-divisional data. The display apparatus includes a data processor including at least a first shift register and a data buffer, and configured to store a first matrix of data corresponding to the frame of image data to the data buffer at time t0, to shift the first matrix of data by m columns by the first shift register to obtain a second matrix of data stored to the data buffer at time t1. The display apparatus further includes an interface connector configured to output the first matrix of data in period T0 and the second matrix of data in period T1 in a same order same as the fixed sequential order respectively over the at least two time-divisional periods T0 and T1 of a unit-time through a driver circuit to a display panel for displaying one frame of image.

This disclosure describes efficient communication of surface texture data between system on a chip (SOC) integrated circuits. An example system includes a first integrated circuit and a second integrated circuit communicatively coupled to the first integrated circuit by a video communication interface. The first integrated generates a superframe in a video frame of the video communication interface for transmission to the second integrated circuit. The superframe includes multiple subframe payloads that carry surface texture data to be updated in the frame and corresponding subframe headers that include parameters of the subframe payloads. The second integrated circuit includes a direct access memory (DMA) controller. The DMA upon receipt of the superframe, writes the surface texture data within each of the subframe payloads directly to an allocated location in memory based on the parameters included in the corresponding one of the subframe headers.

This disclosure describes efficient communication of surface texture data between system on a chip (SOC) integrated circuits. An example system includes a first integrated circuit and a second integrated circuit communicatively coupled to the first integrated circuit by a video communication interface. The first integrated generates a superframe in a video frame of the video communication interface for transmission to the second integrated circuit. The superframe includes multiple subframe payloads that carry surface texture data to be updated in the frame and corresponding subframe headers that include parameters of the subframe payloads. The second integrated circuit includes a direct access memory (DMA) controller. The DMA upon receipt of the superframe, writes the surface texture data within each of the subframe payloads directly to an allocated location in memory based on the parameters included in the corresponding one of the subframe headers.

A method and system for handling frame dropping during playback of a PPT file. The method comprises operating the DXGI screen capturing module to acquire a prepositioned frame in a graphics card cache (S100); acquiring screen data according to the prepositioned frame (S200); monitoring the screen data and timing a duration in which the screen data does not change (S300); and modifying the screen data when the duration exceeds a preset threshold (S400); performing screen capture by the DXGI screen capturing module when the screen data changes (S500). During the whole process, when the duration in which the screen data does not change exceeds the preset threshold, the screen data is actively modified, so that the frame dropping that occurs when there is no change in the screen data may be avoided, thereby enabling effective handling of the frame dropping during playback of the PPT file.

The invention provides a technique for targeted scaling of the voltage and/or frequency of a processor included in a computing device. One embodiment involves scaling the voltage/frequency of the processor based on the number of frames per second being input to a frame buffer in order to reduce or eliminate choppiness in animations shown on a display of the computing device. Another embodiment of the invention involves scaling the voltage/frequency of the processor based on a utilization rate of the GPU in order to reduce or eliminate any bottleneck caused by slow issuance of instructions from the CPU to the GPU. Yet another embodiment of the invention involves scaling the voltage/frequency of the CPU based on specific types of instructions being executed by the CPU. Further embodiments include scaling the voltage and/or frequency of a CPU when the CPU executes workloads that have characteristics of traditional desktop/laptop computer applications.

The present application discloses display apparatus for displaying image based on time-divisional data. The display apparatus includes a data processor including at least a first shift register and a data buffer, and configured to store a first matrix of data corresponding to the frame of image data to the data buffer at time t0, to shift the first matrix of data by m columns by the first shift register to obtain a second matrix of data stored to the data buffer at time t1. The display apparatus further includes an interface connector configured to output the first matrix of data in period T0 and the second matrix of data in period T1 in a same order same as the fixed sequential order respectively over the at least two time-divisional periods T0 and T1 of a unit-time through a driver circuit to a display panel for displaying one frame of image.

A display device includes a plurality of pixels, and a plurality of data lines connected to the plurality of pixels; a data driver for transmitting a data voltage to the data line; and a signal controller for receiving input image signals from the outside and outputting a digital image signal to the data driver. The signal controller includes an adjacent image signal compensator for comparing input gray data of the input image signals to be continuously input to the data line and generating adjacent image signal compensation data based on the comparison, and a pixel characteristic compensator for generating pixel characteristic compensation data according to a characteristic of a pixel to be displayed.

An electronic device is provided. The electronic device includes a first housing including a first surface and a second surface faced away from the first surface, a second housing including a third surface and a fourth surface faced away from the third surface, a first display including a folding part rotatably connecting a side surface of the first housing and a side surface of the second housing facing the side surface of the first housing, the first display being disposed on the first surface and the third surface across the folding part, a second display disposed on the second surface of the first housing, at least one memory storing instructions, and at least one processor.

An electronic device that includes a memory and a plane circuit is described. The memory outputs a first alpha data value and a first pixel data value, then outputs a second alpha data value and a second pixel data value, then stores a third pixel data value. The plane circuit outputs a request signal for the third pixel data value, based on whether the first alpha data value and the second alpha data value are equal to a reference value and whether the first pixel data value corresponds to the third pixel data value.