A multiple input multi-media switch box allowing for communication between video surveillance cameras, a multi-media player, and a public view monitor for seamless transitions between frames and or advertising media is disclosed. The switch box displays a first video surveillance content on the PVM for a predetermined time, the converter switch freezes the last frame on the first video surveillance image and displays advertising media while buffering the new input from a second video surveillance, then the converter switch releases and displays the new input from the second video surveillance video.

An image display device includes an image input unit into which an image signal from an image signal source is input; a memory; a writing unit that writes at a first frequency an image signal input into the image input unit into the memory; a reading unit that reads at a second frequency higher than the first frequency an image signal written in the memory; an image output unit that outputs an image signal read by the reading unit to a display unit; and an image interpolation unit that interpolates an image to be output to the display unit.

A power saving control apparatus applied to a display driving circuit is disclosed. The power saving control apparatus includes a data analysis unit, a bias control unit and a charge sharing unit. The bias control unit is used to perform bias control. The charge sharing unit is used for charge sharing. The data analysis unit is coupled to the bias control unit and the charge sharing unit respectively. The data analysis unit instantly analyzes the display data to generate an instant analysis result and dynamically adjust the setting of bias and slew rate of the bias control unit according to the instant analysis result. The data analysis unit can dynamically adjust the setting of charge sharing range and charge sharing group number needed to be performed by the charge sharing unit according to the instant analysis result.

An electronic device is provided. The electronic device includes a first housing including a first surface and a second surface faced away from the first surface, a second housing including a third surface and a fourth surface faced away from the third surface, a first display including a folding part rotatably connecting a side surface of the first housing and a side surface of the second housing facing the side surface of the first housing, the first display being disposed on the first surface and the third surface across the folding part, a second display disposed on the second surface of the first housing, at least one memory storing instructions, and at least one processor.

An electronic device includes a display panel; a processor; and display driving integrated circuitry (DDIC). The DDIC is configured to control the display panel and includes an internal memory. The DDIC is configured to receive, from the processor while the processor operates in an active state, a first content including a plurality of images to be displayed based on a specified order through the display panel while the processor operates in a low-power state; store the first content in the internal memory; change a timing for outputting a signal corresponding to a state capable of receiving a second content based on a change of a location in which an image among the plurality of images is displayed through the display panel while the processor operates in the low-power state; and output the signal to the processor based on the changed timing.

The present disclosure provides apparatuses including display driver circuits and operating methods thereof. In some embodiments, an electronic device includes a display panel, a nonvolatile memory, and a display driver circuit configured to receive frame data through a video interface channel, generate compensated frame data by compensating for the frame data by using compensation data, and send the compensated frame data to the display panel. The display driver circuit includes a display memory configured to store the compensation data, a compensation circuit configured to generate the compensated frame data from the frame data, a buffer memory, and a backup controller configured to monitor a status of the compensation circuit, and, when the compensation circuit is in an idle state, read partial data among the compensation data from the display memory, and write data present in the buffer memory in the nonvolatile memory.

The invention provides a technique for targeted scaling of the voltage and/or frequency of a processor included in a computing device. One embodiment involves scaling the voltage/frequency of the processor based on the number of frames per second being input to a frame buffer in order to reduce or eliminate choppiness in animations shown on a display of the computing device. Another embodiment of the invention involves scaling the voltage/frequency of the processor based on a utilization rate of the GPU in order to reduce or eliminate any bottleneck caused by slow issuance of instructions from the CPU to the GPU. Yet another embodiment of the invention involves scaling the voltage/frequency of the CPU based on specific types of instructions being executed by the CPU. Further embodiments include scaling the voltage and/or frequency of a CPU when the CPU executes workloads that have characteristics of traditional desktop/laptop computer applications.

This application is directed to a method of managing processing capability of a server system having one or more processing cores that further include multiple processing slices. Upon receiving requests to initiate online gaming sessions, the server system allocates each processing slice of the processing cores to a subset of the online gaming sessions to be executed thereon. A first processing slice is allocated to a first subset of the online gaming sessions including a first gaming session and a second gaming session. At the first processing slice, a time-sharing processing schedule is determined for the first subset of the online gaming sessions. In accordance with the time-sharing processing schedule, the first and second gaming sessions share a duty cycle of the first processing slice, and are executed dynamically and in parallel according to real-time data processing need of the first and second gaming sessions.

A direct memory access (DMA) buffer section configured to store data in a plurality of storage regions in units of DMA transfers, a buffer control section configured to output a first writing permission signal for permitting the DMA transfer on the basis of presence or absence of a free storage region, a smoothing buffer control section configured to output a second writing permission signal for permitting the DMA transfer within a predetermined period, a buffer writing control section configured to execute the DMA transfer according to the first writing permission signal and the DMA transfer according to the second writing permission signal and stored the data to the free storage region, and a buffer reading control section configured to sequentially read the data for each storage region, wherein a predetermined amount of data sequentially acquired by a plurality of DMA transfers is output as a transfer unit.

An electronic device may include a display panel and an image data source designed to determine a differing region in the image frame by comparing source image data and image data corresponding with a previous image frame. The electronic device may also include a display pipeline between the image data source and the display panel. The display pipeline may include image processing circuitry to convert image data from a source space to a display space and image processing circuitry to spatially process the image data. The display pipeline may determine a crop region by converting the differing region to the display space and determine a partial frame region, based on the image data to be spatially processed, by the image processing circuitry. The display pipeline may also determine and retrieve a fetch region smaller than the image frame by converting the partial frame region to the source space.