Systems, devices, and methods for generating, processing, assembling, and/or formatting data for display are described. Example display controllers are described in which image data is stored in a framebuffer, and a compositor selectively retrieves portions of the image data. At least one P-operator produces lines of intermediate P-operated data by performing at least one intra-line operation on the image data retrieved by the compositor, such as repeating or reordering pixels of the image data. A Q-operator produces a stream of pixel data by performing inter-line operations on the intermediate P-operated data, such as interpolating between lines of the P-operated data. A display is driven according to the stream of pixel data.

A display device includes a display panel configured to display images, a data driver configured to supply data voltages to the display panel, and a controller configured to control the data driver, wherein the controller operates in a normal mode having normal driving conditions and a power saving mode having driving conditions for reducing power consumption and lowers a driving frequency and an environment of an interface connected to the data driver as compared to a driving frequency and an interface environment in the normal mode when operating in the power saving mode.

A display driving device and a control method thereof, and a display device. The control method includes: generating, by the master processing chip, a read/write synchronization signal, and receiving, by each of the slave processing chip, the read/write synchronization signal; in response to the read/write synchronization signal, caching, by the master processing chip, the received display data of the current to-be-displayed frame image into the frame address of the corresponding memory, reading and processing cached display data of a previous to-be-displayed frame image and transmitting the processed display data; and in response to the read/write synchronization signal, caching synchronously, by each of the slave processing chip, the received display data of the current to-be-displayed frame image into the frame address of the corresponding memory, and reading and processing synchronously cached display data of the previous to-be-displayed frame image and transmitting the processed display data.

An example embodiment provides a display driver integrated circuit, including: a memory including a plurality of pieces of driving information corresponding to a plurality of pieces of display mode information, the plurality of display mode information regarding a method of processing an image signal; a signal controller including a buffer, the signal controller configured to receive display mode information and image signals from a host, retrieve driving information corresponding to the display mode information among the plurality of pieces of driving information from the memory, the plurality of pieces of driving information including the driving information, write the driving information in the buffer, and convert the image signal into image data based on the driving information written in the buffer; and a data driver configured to generate a plurality of data signals based on the image data.

A display system may include a memory external to a pixel that stores a first digital data value, a memory internal to the pixel that stores a second digital data signal, where a combination of the first digital data signal and the second digital data signal may indicate a target gray level assigned to the pixel for a particular image frame. The pixel may be driven for a first duration of time according to the first digital data signal and for a second duration of time according to the second digital data signal.

Systems, devices, and methods for generating, processing, assembling, and/or formatting data for display are described. Example display controllers are described in which image data is stored in a framebuffer, and a compositor selectively retrieves portions of the image data. At least one P-operator produces lines of intermediate P-operated data by performing at least one intra-line operation on the image data retrieved by the compositor, such as repeating or reordering pixels of the image data. A Q-operator produces a stream of pixel data by performing inter-line operations on the intermediate P-operated data, such as interpolating between lines of the P-operated data. A display is driven according to the stream of pixel data.

According to an example aspect of the present invention, there is provided an apparatus comprising a first processing core configured to generate first control signals and to control a display by providing the first control signals to the display via a first display interface, a second processing core configured to generate second control signals and to control the display by providing the second control signals to the display via a second display interface, and the first processing core being further configured to cause the second processing core to enter and leave a hibernation state based at least partly on a determination, by the first processing core, concerning an instruction from outside the apparatus.

A display driving device, a control method therefor, and a display apparatus. The control method comprises: a main processing chip generates a read-write synchronization signal when buffering received display data, and each secondary processing chip receives the read-write synchronization signal (S202); in response to the read-write synchronization signal, the main processing chip buffers the received display data of the current frame image to be displayed to the frame address of a corresponding memory, and performs reading and processing on the buffered display data of a previous frame image to be displayed and then transmits to a display panel, and in response to the read-write synchronization signal, each secondary processing chip synchronously buffers the received display data of the current frame image to be displayed to the frame address of the corresponding memory, and synchronously performs reading and processing on the buffered display data of the previous frame image to be displayed and then transmits to the display panel (S203). By means of the read-write synchronization signal, the main processing chip and all the secondary processing chips are controlled to control the storage and read operations of the memory, and thus, the present invention can avoid that the processing chips share the frame address of the memory, and further can avoid the problem of abnormal image display due to multiple asynchronous processing chips.

In one embodiment, an apparatus having an integrated circuit made of substrate, at least three light emitters arranged on the substrate, and driver circuitry located on the integrated circuit, the driver circuitry to drive an ultra low persistence display to remove ghosting and nausea.

A display system may include a memory external to a pixel that stores a first digital data value, a memory internal to the pixel that stores a second digital data signal, where a combination of the first digital data signal and the second digital data signal may indicate a target gray level assigned to the pixel for a particular image frame. The pixel may be driven for a first duration of time according to the first digital data signal and for a second duration of time according to the second digital data signal.