The disclosure discloses a data processing method and device for a Light emitting diode (LED) Television (TV), and an LED TV, wherein the data processing device includes: a signal processing chip configured to perform mode conversion on a received TV signal so as to obtain a first video signal of a preset mode; and a video processing chip connected to the signal processing chip and configured to perform clock synchronization processing on the first video signal so as to obtain a second video signal and output the second video signal to an LED display. By means of the disclosure, the problem in the prior art that an LED TV can only display a TV signal of a single mode is solved, thereby achieving the effect that the LED TV can display videos of various modes and various formats.

Systems, apparatuses, and methods for prefetching data by a display controller. From time to time, a performance-state change of a memory are performed. During such changes, a memory clock frequency is changed for a memory subsystem storing frame buffer(s) used to drive pixels to a display device. During the performance-state change, memory accesses may be temporarily blocked. To sustain a desired quality of service for the display, a display controller is configured to prefetch data in advance of the performance-state change. In order to ensure the display controller has sufficient memory bandwidth to accomplish the prefetch, bandwidth reduction circuitry in clients of the system are configured to temporarily reduce memory bandwidth of corresponding clients.

A display device includes a memory, a timing controller including a scaler, and a processor, wherein the processor is configured to generate, via the scaler, a first sync signal based on an input timing of at least one piece of background image data, generate, via the scaler, a second sync signal based on an input timing of at least one piece of region of interest (ROI) image data, transmit, to the scaler, the at least one piece of background image data output from the memory during a first period according to the first sync signal, and transmit, to the scaler, the at least one piece of ROI image data output from the memory during a second period according to the second sync signal.

Circuitry for adjusting luminance of a display device is provided. The circuitry includes a non-volatile memory array having a plurality memory cells configured to store luminance data of the display device, and a luminance adjusting circuit configured to receive image data to be displayed on the display device. The luminance adjusting circuit is coupled directly to the non-volatile memory array to receive the luminance data of the display device from the non-volatile memory array and adjust the image data based on the luminance data of the display device.

The disclosure provides an image data transmission device including: receiving sub-circuit, writing control component, and reading control component. The disclosure further provides an image data transmission method, including: in response to the receiving sub-circuit being in locked state, receiving, by receiving sub-circuit, image data sent by a mainboard, and writing, according to a first frame synchronous signal, the image data received from the mainboard in each clock cycle of the first frame synchronous signal into a frame of a memory, reading, according to a second frame synchronous signal, a frame from the memory in each clock cycle of the second frame synchronous signal; sending each frame read from the memory to a display component; and in response to the receiving sub-circuit being in unlocked state, stopping writing the image data into the memory. The disclosure further provides an electronic apparatus, a computer-readable medium and a display system.

An example embodiment provides a display driver integrated circuit, including: a memory including a plurality of pieces of driving information corresponding to a plurality of pieces of display mode information, the plurality of display mode information regarding a method of processing an image signal; a signal controller including a buffer, the signal controller configured to receive display mode information and image signals from a host, retrieve driving information corresponding to the display mode information among the plurality of pieces of driving information from the memory, the plurality of pieces of driving information including the driving information, write the driving information in the buffer, and convert the image signal into image data based on the driving information written in the buffer; and a data driver configured to generate a plurality of data signals based on the image data.

An integrated architecture includes an application processor adapted to acquire an unprocessed image, and apply an overdrive function and a frame rate conversion function for the unprocessed image to generate a processed image when a source frame rate and a panel frame rate are different. The integrated architecture of the present invention does not dispose the memory in the display drive integrated circuit, and the memory of the application processor which is cooperated with the foresaid ramlsss display drive integrated circuit can support both the overdrive function and the frame rate conversion function, so that the integrated architecture can have advantages of the preferred hardware cost, the preferred picture quality, the preferred power consumption and the preferred image control.