Systems and methods are disclosed for detection of a selected signal pattern, such as a servo sector preamble, and for frequency offset determination. A circuit may be configured to divide a signal into detection windows of a selected size, and sample the signal a selected number of times within each detection window. The circuit may then determine an error value for each detection window based on values of the samples for each detection window, and determine the preamble is detected when a threshold number of most-recently sampled detection windows have error values below a threshold value. The circuit may then organize the sample values corresponding to the preamble into groups, and calculate phase estimates representing a phase at which the groups were sampled. The circuit may determine a frequency offset based on the phase estimates, and modulate the sampling frequency according to the frequency offset.

Provided is an optical medium reproducing apparatus including: a detection unit that divides a luminous flux into a plurality of regions including a first region and a second region which are different in a position in a radial direction and/or a tangential direction, and combines a plurality of detection signals in correspondence with the amount of light that is incident to each of the plurality of regions with combination patterns which are selected to form signals of a plurality of channels; a multi-input equalizer unit that includes a plurality of equalizer units to which the signals of the plurality of channels are respectively supplied, computes outputs of the plurality of equalizer units, and outputs the resultant value as an equalization signal; and a binarization unit that performs binarization processing with respect to the equalization signal to obtain binary data. An addition signal channel including a constant multiplication of detection signals of the first region and the second region is included in at least one of the combination patterns.

In one embodiment, a system for processing data includes a processor and logic integrated with and/or executable by the processor. The logic is configured to detect and track positive peak amplitudes and negative peak amplitudes of a readback waveform during data reading using a tracking threshold module, and to detect and track positive peak amplitudes and negative peak amplitudes of the readback waveform during the data reading at an input to an equalizer using a second tracking threshold module in response to reading a data set separator (DSS). Moreover, the logic is configured to perform asymmetry compensation on the data using an asymmetry compensator in an asymmetry compensation loop based on input from the tracking threshold module when not reading a DSS and based on input from the second tracking threshold module when reading a DSS, an output of the asymmetry compensator being provided to the equalizer.

The presently disclosed technology teaches integrating disc drive electronics into a transducer head. Decreased electrical transit times and data processing times can be achieved by placing the electronics on or within the transducer head because electrical connections may be made physically shorter than in conventional systems. The electronics may include one or more of a control system circuit, a write driver, and/or a data buffer. The control system circuit generates a modified clock signal that has a fixed relation to phase and frequency of a bit-detected reference signal that corresponds to positions of patterned bits on the disc. The write driver writes outgoing data bits received from an external connection to off-head electronics directly to the writer synchronized with the modified clock signal. The data buffer stores and converts digital data bits sent from the off-head electronics to an analog signal that is synchronized with the modified clock signal.

Technology for improved data detection using machine learning may include a method in which an analog read signal comprising data read from a non-transitory storage medium of the data storage device is received. The analog read signal is processed into a plurality of digital samples. A digital sample from the plurality of digital samples is classified into a category from a plurality of categories using a machine learning algorithm for at least some of the plurality of digital samples. The plurality of digital samples is then decoded based on at least some of the predicted categories.

A divider and buffer circuit uses a receive command to initiate a reset of buffer circuitry prior to restarting to avoid a metastable state. For example, the divider and buffer circuit includes a first buffer circuit, a second buffer circuit, and a reset circuit. The reset circuit receives a command and provide a pulse on a reset signal in response to the command. In response to the reset pulse, the first buffer circuit provides a first divided clock signal having a first logical value based on respective logical values of received complementary clock signals and the second buffer circuit provides a second divided clock signal having a second logical value based on the respective logical values of the complementary clock signals. The command is a CAS SYNC command, in some examples.

Technology for improved data detection using machine learning may include a method in which an analog read signal comprising data read from a non-transitory storage medium of the data storage device is received. The analog read signal is processed into a plurality of digital samples. A digital sample from the plurality of digital samples is classified into a category from a plurality of categories using a machine learning algorithm for at least some of the plurality of digital samples. The plurality of digital samples is then decoded based on at least some of the predicted categories.

Systems and methods are disclosed for hardware-based read sample averaging in a data storage device. In one example, a read channel circuit including a buffer memory is configured to receive a read instruction to read a selected sector, obtain detected sample values for the selected sector, and determine whether the read instruction corresponds to a re-read operation for the selected sector based on determining whether there are stored samples for the selected sector already stored to a locked buffer entry of the buffer memory. When there are stored sample values stored to the locked buffer entry, the example read channel circuit determines the re-read operation is occurring, and performs read sample averaging based on the detected sample values and the stored sample values to produce averaged sample values. Other examples and configurations are also described.

A method for monitoring working states of hard disks of a system of hard disks in a hard disk module includes a hard disk controller and a complex programmable logic device (CPLD). The hard disk controller and CPLD communicate with the hard disk module. The CPLD receives output signals from the hard disk controller and determines whether rise and fall changes in a clock signal of each output signal are steady. When a level change of the clock signal of one output signal is steady, the CPLD decodes the one output signal. When a level change of the clock signal of one output signal is not steady, the CPLD will stop decoding the one output signal. A related method is also provided.

The presently disclosed technology teaches integrating disc drive electronics into a transducer head. Decreased electrical transit times and data processing times can be achieved by placing the electronics on or within the transducer head because electrical connections may be made physically shorter than in conventional systems. The electronics may include one or more of a control system circuit, a write driver, and/or a data buffer. The control system circuit generates a modified clock signal that has a fixed relation to phase and frequency of a bit-detected reference signal that corresponds to positions of patterned bits on the disc. The write driver writes outgoing data bits received from an external connection to off-head electronics directly to the writer synchronized with the modified clock signal. The data buffer stores and converts digital data bits sent from the off-head electronics to an analog signal that is synchronized with the modified clock signal.