Examples are disclosed that relate to reading stored data. The method comprises obtaining a representation of a measurement performed on a data-storage medium, the representation being based on a previously recorded pattern of data encoded in the data-storage medium in a layout that defines a plurality of data locations. The method further comprises inputting the representation into a data decoder comprising a trained machine-learning function, and obtaining from the data decoder, for each data location of the layout, a plurality of probability values, wherein each probability value is associated with a corresponding data value and represents the probability that the corresponding data value matches the actual data value in the previously recorded pattern of data at a same location in the layout.

A divider and buffer circuit uses a receive command to initiate a reset of buffer circuitry prior to restarting to avoid a metastable state. For example, the divider and buffer circuit includes a first buffer circuit, a second buffer circuit, and a reset circuit. The reset circuit receives a command and provide a pulse on a reset signal in response to the command. In response to the reset pulse, the first buffer circuit provides a first divided clock signal having a first logical value based on respective logical values of received complementary clock signals and the second buffer circuit provides a second divided clock signal having a second logical value based on the respective logical values of the complementary clock signals. The command is a CAS SYNC command, in some examples.

A card reader includes a writing coil that is provided to a magnetic head for recording magnetic data in a magnetic card, and a drive circuit that supplies a write current to the writing coil. The drive circuit is a chopping circuit that supplies a chopping current, on/off of which is switched in a specified cycle, as the write current to the writing coil. An on/off cycle of the chopping current is a cycle in which a length of a magnetized pattern in a recording direction is shorter than a reading gap formed in a core around which the writing coil is wound or a core around which a reading coil being separately provided from the writing coil is wound, the magnetized pattern in the recording direction being formed in the magnetic card by the chopping current in a period including one each of the on and the off.

The presently disclosed technology teaches integrating disc drive electronics into a transducer head. Decreased electrical transit times and data processing times can be achieved by placing the electronics on or within the transducer head because electrical connections may be made physically shorter than in conventional systems. The electronics may include one or more of a control system circuit, a write driver, and/or a data buffer. The control system circuit generates a modified clock signal that has a fixed relation to phase and frequency of a bit-detected reference signal that corresponds to positions of patterned bits on the disc. The write driver writes outgoing data bits received from an external connection to off-head electronics directly to the writer synchronized with the modified clock signal. The data buffer stores and converts digital data bits sent from the off-head electronics to an analog signal that is synchronized with the modified clock signal.

Deterioration of convergence performance or operational stability due to an increase in constraint length is suppressed when coefficients are updated, so that decoding performance is improved. A decoding device according to the present technology includes an adaptive equalization unit that performs adaptive equalization, an adaptive maximum likelihood decoding unit that causes an identification point of maximum likelihood decoding to adaptively follow a characteristic of an input signal, a target waveform generation unit that, by convoluting a partial response coefficient into a decoded value, generates an equalization target waveform of the adaptive equalization which is performed by the adaptive equalization unit, an error signal generation unit that generates, as an equalization error signal, an error signal between the equalization target waveform and an equalized signal, and a coefficient updating unit that, through least-square-method computation for minimizing a correlation between the decoded value and the equalization error signal, updates the partial response coefficient which is used by the target waveform generation unit to generate the equalization target waveform.

Example redundant array of independent disks (RAID) storage systems and methods provide rebuild of logical data groups in priority order. Storage devices are configured as a storage array for storing logical data groups distributed among the storage devices. The logical data groups are written in a configuration of RAID stripes in the storage devices. A logical group index includes a logical group map for each logical data group and identifies corresponding logical blocks. When a storage device fails, the rebuild queue is ordered based on the priority of the logical data groups and rebuild to the replacement storage device is completed in the priority order.

Provided are an apparatus and a method for generating a reproduction signal with reduced laser noise. There are provided a photodetector (PD) that irradiates a disk with laser light and outputs a signal based on a reflected light from the disk, a front monitor that outputs a reference signal based on an emitted light of a laser diode, and a data detection processing unit to which an output signal of the PD is input to generate a reproduction signal. The data detection processing unit includes a reproduction signal adaptive equalizer that outputs an equalization signal by adaptive equalization processing based on the PD output signal, and a laser noise adaptive equalizer that outputs the equalization signal by the adaptive equalization processing based on a laser noise signal, and generates the reproduction signal in which the laser noise is reduced on the basis of an arithmetic operation result of the output of the reproduction signal adaptive equalizer and the output of the laser noise adaptive equalizer.

Systems and methods are disclosed for hardware-based read sample averaging in a data storage device. In one example, a read channel circuit including a buffer memory is configured to receive a read instruction to read a selected sector, obtain detected sample values for the selected sector, and determine whether the read instruction corresponds to a re-read operation for the selected sector based on determining whether there are stored samples for the selected sector already stored to a locked buffer entry of the buffer memory. When there are stored sample values stored to the locked buffer entry, the example read channel circuit determines the re-read operation is occurring, and performs read sample averaging based on the detected sample values and the stored sample values to produce averaged sample values. Other examples and configurations are also described.

A divider and buffer circuit uses a receive command to initiate a reset of buffer circuitry prior to restarting to avoid a metastable state. For example, the divider and buffer circuit includes a first buffer circuit, a second buffer circuit, and a reset circuit. The reset circuit receives a command and provide a pulse on a reset signal in response to the command. In response to the reset pulse, the first buffer circuit provides a first divided clock signal having a first logical value based on respective logical values of received complementary clock signals and the second buffer circuit provides a second divided clock signal having a second logical value based on the respective logical values of the complementary clock signals. The command is a CAS SYNC command, in some examples.

A divider and buffer circuit uses a receive command to initiate a reset of buffer circuitry prior to restarting to avoid a metastable state. For example, the divider and buffer circuit includes a first buffer circuit, a second buffer circuit, and a reset circuit. The reset circuit receives a command and provide a pulse on a reset signal in response to the command. In response to the reset pulse, the first buffer circuit provides a first divided clock signal having a first logical value based on respective logical values of received complementary clock signals and the second buffer circuit provides a second divided clock signal having a second logical value based on the respective logical values of the complementary clock signals. The command is a CAS SYNC command, in some examples.