The present disclosure describes aspects of codeword interleaving for magnetic storage media. In some aspects, segments of a codeword are spread or interleaved across multiple sectors of magnetic storage media. Data for one or more codewords may be received by a read channel and, for each codeword, a respective indicator is selected or received. The indicator may indicate which partitions of the multiple sectors that segments of one of the codewords are to be written. The data is then encoded to provide the codewords and segments of the codewords are placed in an interleaver based on the respective indicator corresponding to the codeword. The codeword segments are written from the interleaver to partitions of the multiple sectors of the magnetic storage media. By so doing, codewords may be spread across multiple sectors, such that a loss of a few sectors does not prevent readback and decoding of the codewords.

Deterioration of convergence performance or operational stability due to an increase in constraint length is suppressed when coefficients are updated, so that decoding performance is improved. A decoding device according to the present technology includes an adaptive equalization unit that performs adaptive equalization, an adaptive maximum likelihood decoding unit that causes an identification point of maximum likelihood decoding to adaptively follow a characteristic of an input signal, a target waveform generation unit that, by convoluting a partial response coefficient into a decoded value, generates an equalization target waveform of the adaptive equalization which is performed by the adaptive equalization unit, an error signal generation unit that generates, as an equalization error signal, an error signal between the equalization target waveform and an equalized signal, and a coefficient updating unit that, through least-square-method computation for minimizing a correlation between the decoded value and the equalization error signal, updates the partial response coefficient which is used by the target waveform generation unit to generate the equalization target waveform.

Apparatuses and methods for phase interpolators are provided. An example apparatus comprises a phase interpolator and a controller coupled to the phase interpolator. The controller is configured to provide a digital timing code to the phase interpolator, and the phase interpolator is configured to apply a correction to the received digital timing code based, at least in part, on phase interpolator error correction data from a data structure containing phase interpolator error correction data.

According to one embodiment, a magnetic disk device includes a magnetic disk including at least one servo zone that includes a first data storage track with a first servo pattern having a first frequency and a second data storage track with a second servo pattern having a second frequency, wherein the first data storage track is located closer to an outer diameter of the magnetic disk than the first data storage track and the first frequency is greater than the second frequency; a magnetic head that faces the magnetic disk; and a zone servo switching unit that switches a servo pattern frequency employed to position the magnetic head in a radial direction based on a radial position of the magnetic head.

The present disclosure describes aspects of constant-density writing for magnetic storage media. In some aspects, a constant-density writer delays transitions between bits within write data to enable constant-density writing. The write data has an initial bit period based on a constant clock signal, which is generated based on the rotation of a media disk. The constant-density writer modifies the write data to generate phase-delayed write data, which has a bit period that is greater than or equal to the initial bit period. To realize this bit period, the constant-density writer changes write phases of bit transitions within the write data. The constant-density writer can also insert stretch bits, filter single-bit transitions, and mitigate glitches within the phase-delayed write data.

In one embodiment, a computer program product includes a computer readable storage medium having program instructions embodied therewith. The computer readable storage medium is not a transitory signal per se. The embodied program instructions are readable/executable by a processor to cause the processor to write, by the processor, data to a storage medium of a data storage system using a partial reverse concatenated modulation code. The partial reverse concatenated modulation code includes encoding the data by applying a C2 encoding scheme prior to encoding the data by applying one or more modulation encoding schemes, followed by encoding the data by applying a C1 encoding scheme subsequent to the encoding of the data with the one or more modulation encoding schemes. Other computer program products for writing data to a storage medium of a data storage system using a partial reverse concatenated modulation code are presented according to more embodiments.

In one embodiment, a system includes a processor, and logic integrated with the processor, executable by the processor, or integrated with and executable by the processor. The logic is configured to cause the processor to write, by the processor, data to a storage medium of a data storage system using a partial reverse concatenated modulation code. The partial reverse concatenated modulation code comprises encoding the data by applying a C2 encoding scheme prior to encoding the data by applying one or more modulation encoding schemes, followed by encoding the data by applying a C1 encoding scheme subsequent to the encoding of the data with the one or more modulation encoding schemes.

A storage device includes a recording medium, a first memory storing first data read from the recording medium, and a controller. The controller searches for read target data in the first data by executing a parity check on second data that is in the first data and starts at a first position, while executing the parity check, determining whether or not an interruption condition is satisfied, storing the second data in a second memory when the parity check completes without the interruption condition being satisfied and a result of a completed parity check satisfies a first condition, and executing a parity check on third data that is in the first data and starts at a second position, responsive to the interruption condition being satisfied and responsive to the result of the completed parity check not satisfying the first condition.

Disclosed is a decoder circuit for a pulse amplitude modulation signal and a method of decoding a pulse amplitude modulation signal. The pulse amplitude modulation signal has a zeroth signal level, a first signal level, a second signal level and a third signal level. The decoder circuit comprises a first decision circuit, and a mapping circuit. The first decision circuit receives the pulse amplitude modulation signal and generates a low output signal for the first and the zeroth signal level, and generates a high output signal for the third and the second signal level. The mapping circuit receives the pulse amplitude modulation signal and generates a low output signal for the second and first signal level, and generates a high output signal for the third and zeroth signal level. Optionally, the decoder circuit comprises a logic circuit. The logic circuit receives the generated signal of the mapping circuit and the generated signal of the first decision circuit and generates a low output signal or a high output signal according to a predetermined truth table.

The card reader includes a peak detector that detects a peak point of a reproduced signal according to a threshold. The peak detector applies, to a first peak value to be determined, a second peak value immediately before the first peak value, a third peak value, which is the second preceding peak value with respect to the first peak value, and a next peak value. When a difference between a first intermediate value, which is a value between the third peak value and the second peak value, and a second intermediate value, which is a value between the second peak value and the first peak value, is greater than or equal to a first difference value, the peak detector ignores a first threshold, and decides the first peak value after confirming that a digital value corresponding to the next peak value has exceeded a second threshold.