Patent classifications
G11B20/14
In-circuit calibration of anti-aliasing filter
An apparatus according to one embodiment includes a hardware based controller that is configured to perform operations. The operations include performing anti-aliasing filtering on each of a plurality of signals, each signal having a frequency that is a different fraction of a frequency of a data read clock. An amplitude is measured of each of the signals after the anti-aliasing filtering. Moreover, the operations include determining whether the measured amplitudes of the signals are within a predefined range. Anti-aliasing settings used during the anti-aliasing filtering are stored in response to a determination that the amplitudes of the signals are within the predefined range. The anti-aliasing settings are changed in response to a determination that the amplitudes of the signals are outside the predefined range.
INFORMATION REPRODUCTION APPARATUS AND INFORMATION REPRODUCTION METHOD
The card reader includes a peak detector that detects a peak point of a reproduced signal according to a threshold. The peak detector applies, to a first peak value to be determined, a second peak value immediately before the first peak value, a third peak value, which is the second preceding peak value with respect to the first peak value, and a next peak value. When a difference between a first intermediate value, which is a value between the third peak value and the second peak value, and a second intermediate value, which is a value between the second peak value and the first peak value, is greater than or equal to a first difference value, the peak detector ignores a first threshold, and decides the first peak value after confirming that a digital value corresponding to the next peak value has exceeded a second threshold.
INFORMATION REPRODUCTION APPARATUS AND INFORMATION REPRODUCTION METHOD
The card reader includes a peak detector that detects a peak point of a reproduced signal according to a threshold. The peak detector applies, to a first peak value to be determined, a second peak value immediately before the first peak value, a third peak value, which is the second preceding peak value with respect to the first peak value, and a next peak value. When a difference between a first intermediate value, which is a value between the third peak value and the second peak value, and a second intermediate value, which is a value between the second peak value and the first peak value, is greater than or equal to a first difference value, the peak detector ignores a first threshold, and decides the first peak value after confirming that a digital value corresponding to the next peak value has exceeded a second threshold.
MAGNETIC DISK DEVICE AND CONTROL METHOD OF MAGNETIC DISK DEVICE
According to one embodiment, a magnetic disk device includes a magnetic disk including at least one servo zone that includes a first data storage track with a first servo pattern having a first frequency and a second data storage track with a second servo pattern having a second frequency, wherein the first data storage track is located closer to an outer diameter of the magnetic disk than the first data storage track and the first frequency is greater than the second frequency; a magnetic head that faces the magnetic disk; and a zone servo switching unit that switches a servo pattern frequency employed to position the magnetic head in a radial direction based on a radial position of the magnetic head.
Method and apparatus for determining read-head deviation using orthogonal preambles
A storage device includes read circuitry having a read head having a detector that outputs signals representing data from a first track and an adjacent track. The read head is subject to off-track excursions during which the read head detects signals from both the first track and an adjacent track. Data on each track includes a preamble including a repeating pattern. The repeating pattern in any first track is orthogonal to the repeating pattern in any track adjacent to the first track. The read circuitry also includes respective Discrete Fourier Transform circuits to identify components in the signals corresponding to respective frequencies characteristic of the repeating pattern on the first track and the repeating pattern on the second track, and computation circuitry to determine from the components a ratio by which the read head is off-track. Corresponding methods are provided for operating such a storage device and for reading data.
Recording medium, recording apparatus, recording method, reproducing apparatus, and reproduction method
There is provided a recording medium, a recording apparatus, a recording method, a reproducing apparatus, and a reproduction method that make it possible to correctly reproduce multilevel codes recorded at high density. A multilevel code of at least three ML values produced by coding user data into a (d,k)-RLL code of the ML values and a particular pattern of the ML values that includes a run of repeated codes which is greater than a maximum run k of the multilevel code are recorded on a recording medium. In addition, reproduction is performed from the recording medium, and the multilevel code is decoded according to the particular pattern. For example, the present technology can be applied to a recording medium, a recording/reproducing apparatus that performs recording on and reproduction from the recording medium, and the like.
IN-CIRCUIT CALIBRATION OF ANTI-ALIASING FILTER
An apparatus according to one embodiment includes a hardware based controller that is configured to perform operations. The operations include performing anti-aliasing filtering on each of a plurality of signals, each signal having a frequency that is a different fraction of a frequency of a data read clock. An amplitude is measured of each of the signals after the anti-aliasing filtering. Moreover, the operations include determining whether the measured amplitudes of the signals are within a predefined range. Anti-aliasing settings used during the anti-aliasing filtering are stored in response to a determination that the amplitudes of the signals are within the predefined range. The anti-aliasing settings are changed in response to a determination that the amplitudes of the signals are outside the predefined range.
IN-CIRCUIT CALIBRATION OF ANTI-ALIASING FILTER
An apparatus according to one embodiment includes a hardware based controller that is configured to perform operations. The operations include performing anti-aliasing filtering on each of a plurality of signals, each signal having a frequency that is a different fraction of a frequency of a data read clock. An amplitude is measured of each of the signals after the anti-aliasing filtering. Moreover, the operations include determining whether the measured amplitudes of the signals are within a predefined range. Anti-aliasing settings used during the anti-aliasing filtering are stored in response to a determination that the amplitudes of the signals are within the predefined range. The anti-aliasing settings are changed in response to a determination that the amplitudes of the signals are outside the predefined range.
1-16 and 1.5-7.5 frequency divider for clock synthesizer in digital systems
A frequency divider unit has a digital frequency divider configured to divide by an odd integer, and a dual-edge-triggered one-shot coupled to double frequency of an output of the digital frequency divider. The frequency divider unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, and 3.5. In embodiments, the frequency divider unit relies on circuit delays to determine an output pulsewidth, and in other embodiments the output pulsewidth is determined from a clock signal. In embodiments, the unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, and 7.5 as well as many integer ratios including 2, 4, 6, and 8. In embodiments, the digital frequency divider is configurable to provide a 50% duty cycle to the one-shot.
SIGNAL PROCESSING APPARATUS AND SIGNAL PROCESSING METHOD
There is provided a signal processing apparatus and a signal processing method capable of allowing data recorded at a high density to be robustly reproduced. A frame sync (FS) is restored by performing maximum likelihood decoding of the FS according to a time-varying trellis with a state and a state transition being limited according to a time, in maximum likelihood decoding of a reproduction signal reproduced from a disk-shaped recording medium, the FS representing a head of a frame, the FS of the frame being arranged at the head of the frame, the FS being recorded at the same positions in a track direction in two adjacent tracks.