A semiconductor package is provided. The semiconductor package includes: a substrate; a first buffer chip and a second buffer chip located on an upper part of the substrate; a plurality of nonvolatile memory chips located on the upper part of the substrate and including a first nonvolatile memory chip and a second nonvolatile memory chip, the first nonvolatile memory chip being electrically connected to the first buffer chip, and the second nonvolatile memory chip being electrically connected to the second buffer chip; a plurality of external connection terminals connected to a lower part of the substrate; and a rewiring pattern located inside the substrate. The rewiring pattern is configured to diverge an external electric signal received through one of the plurality of external connection terminals into first and second signals, transmit the first signal to the first buffer chip, and transmit the second signal to the second buffer chip.

An integrated circuit includes a plurality of memory cells, a first pair of complementary data lines, and a second pair of complementary data lines. The plurality of memory cells include a first array of memory cells and a second array of memory cells. The first pair of complementary data lines are coupled to the first array of memory cells. The second pair of complementary data lines are different from the first pair of complementary data lines and are coupled to the second array of memory cells. A number of memory cells in the first array of memory cells is different from a number of memory cells in the second array of memory cells.

Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.

Methods, systems, and devices for apparatus for differential memory cells are described. An apparatus may include a pair of memory cells comprising a first memory cell and a second memory cell, a word line coupled with the pair of memory cells and a plate line coupled with the pair of memory cells. The apparatus may further include a first digit line coupled with the first memory cell and a sense amplifier and a second digit line coupled with the second memory cell and the sense amplifier. The apparatus may include a select line configured to couple the first digit line and the second digit line with the sense amplifier.

A method for forming a semiconductor device includes the following operations. A stacked structure is provided, which includes a substrate, and sacrificial layers and semiconductor layers alternately stacked on surface of the substrate. Multiple first grooves and semiconductor pillars extending in first direction are included in the sacrificial layers and the semiconductor layers. Word line pillars are formed in second direction, intersect with the semiconductor pillars and surround the semiconductor pillars. Sources and drains are formed respectively on either side of the semiconductor pillars surrounded by the word line pillars by an epitaxial growth process. Bit lines are formed on a side of the sources or the drains, are connected with same, and extend in third direction. The first, second and third directions are pairwise perpendicular. Capacitors are formed on a side of the sources or the drains where the bit lines are not formed to form a semiconductor device.

Embodiments provide a method for fabricating a semiconductor structure and a structure thereof. The method includes: providing a substrate; forming, on the substrate, semiconductor channels arranged in an array along a first direction and a second direction; forming bit lines extending along the first direction, wherein the bit lines are positioned in the substrate, and each of the bit lines is electrically connected to the semiconductor channels arranged along the first direction; forming word lines extending along the second direction, wherein the word lines wrap part of side surfaces of the semiconductor channels arranged along the second direction, where one of the word lines includes two sub word lines arranged at intervals along the first direction, and the sub word lines cover part of opposite side surfaces of the semiconductor channels along the first direction; and forming isolation structures positioned between adjacent word lines and between adjacent sub word lines.

Embodiments relate to a semiconductor device and a forming method. The semiconductor device includes: a substrate; a memory array positioned on the substrate and at least including memory cells spaced along a first direction, each of the memory cells including a transistor, the transistor including a gate electrode, channel regions distributed on two opposite sides of the gate electrode along a third direction, and a source region and a drain region distributed on two opposite sides of each of the channel regions along a second direction, the first direction and the third direction being directions parallel to a top surface of the substrate, the first direction intersecting with the third direction, and the second direction being a direction perpendicular to the top surface of the substrate; and a word line extending along the first direction and continuously electrically connected to the gate electrodes spaced along the first direction.

Embodiments of the disclosure provide a semiconductor structure, a method for manufacturing the same and a memory. The semiconductor structure includes a plurality of active pillars and a plurality of conductor lines. Each of the conductor lines includes a plurality of metal layers located in a gap between two adjacent active pillars and a metal compound layer partially surrounding the plurality of active pillars.

The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.

Provided is an anti-fuse memory circuit. The anti-fuse memory circuit includes a memory array, a bit line (BL), and a word line (WL); an anti-fuse memory cell (FsBIn) electrically connected to the bit line (BL) through a first switch transistor (1Add); a second switch transistor (2Add) configured to connect the bit line (BL) to a transmission wire (100); a third switch transistor (3Add) configured to discharge the transmission wire (100); a reading module (102) including a first input end (+) connected to the transmission wire (100), a second input end (−) for receiving a reference voltage (VTRIP), and a sampling input end (C) for receiving a sampling signal (CLK); and a compensation module (101), connected to the third switch transistor (3Add) and configured to slow down a drop speed of a voltage at the transmission wire (100).