Discussed herein are systems and methods for protecting against transistor degradation in a high-voltage (HV) shifter to transfer an input voltage to an access line, such as a global wordline. An embodiment of a memory device comprises memory cells and a HV shifter circuit that includes a signal transfer circuit, and first and second HV control circuits. The signal transfer circuit includes a P-channel transistor to transfer a high-voltage input to an access line. The first HV control circuit couples a bias voltage to the P-channel transistor for a first time period, and the second HV control circuit couples a stress-relief signal to the P-channel transistor for a second time period, after the first time period, to reduce degradation of the P-channel transistor. The transferred high voltage can be used to charge the access line to selectively read, program, or erase memory cells.

A memory device includes rows and columns of memory cells, word lines each connected to a memory cell row, bit lines each connected to a memory cell column, a word line driver connected to the word lines, a bit line driver connected to the bit lines, word line switches each disposed on one of the word lines for selectively connecting one memory cell row to the word line driver, and bit line switches each disposed on one of the bit lines for selectively connecting one memory cell column to the bit line driver. A controller controls the word line switches to connect only some of the rows of memory cells to the word line driver at a first point in time, and controls the bit line switches to connect only some of the columns of memory cells to the bit line driver at a second point in time.

A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

Operations with reduced current overall are performed on single thyristor memory cells forming a volatile memory cell cross-point array. A first voltage is applied across a first group of memory cells for the operation and a lower second voltage is applied across other groups of memory cells. The first voltage is then applied across a second group of memory cells while the second voltage is applied across the other groups including the first group of memory cells and repeated until the operations covers all the groups.

To provide a magnetic memory for storing multi-level information capable of reading while sufficiently securing a read margin. Provided is a magnetic memory including: first and second magnetic storage elements that are provided between a first wiring and a second wiring crossing each other, and are electrically connected in series; a third wiring electrically connected between the first and second magnetic storage elements; a first determination unit that determines a magnetization state of the first magnetic storage element on the basis of a current flowing to the first magnetic storage element through the third wiring; and a second determination unit that determines a magnetization state of the second magnetic storage element on the basis of a current flowing to the first and second magnetic storage elements through the first wiring, in which the determination state of the second determination unit is changed on the basis of the determination result of the first determination unit.

To provide a magnetic memory for storing multi-level information capable of reading while sufficiently securing a read margin. Provided is a magnetic memory including: first and second magnetic storage elements that are provided between a first wiring and a second wiring crossing each other, and are electrically connected in series; a third wiring electrically connected between the first and second magnetic storage elements; a first determination unit that determines a magnetization state of the first magnetic storage element on the basis of a current flowing to the first magnetic storage element through the third wiring; and a second determination unit that determines a magnetization state of the second magnetic storage element on the basis of a current flowing to the first and second magnetic storage elements through the first wiring, in which the determination state of the second determination unit is changed on the basis of the determination result of the first determination unit.

A storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a variable resistance layer disposed between the first conductive layer and the second conductive layer, and a switching layer disposed between the second conductive layer and the third conductive layer. The second conductive layer is disposed between the first conductive layer and the third conductive layer. The switching layer includes a first area, a second area, and a third area disposed between the first area and the second area. The first area includes a first element selected from Sn, Ga, Zn, Ta, Ti, and In, and O or N. The second area includes a second element selected from Sn, Ga, Zn, Ta, Ti, and In, and O or N. The third area includes a third element selected from Zr, Y, Ce, Hf, Al, Mg, and Nb, O or N, and a metal element selected from Te, Sb, Bi, Ti, and Zn.

A storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a variable resistance layer disposed between the first conductive layer and the second conductive layer, and a switching layer disposed between the second conductive layer and the third conductive layer. The second conductive layer is disposed between the first conductive layer and the third conductive layer. The switching layer includes a first area, a second area, and a third area disposed between the first area and the second area. The first area includes a first element selected from Sn, Ga, Zn, Ta, Ti, and In, and O or N. The second area includes a second element selected from Sn, Ga, Zn, Ta, Ti, and In, and O or N. The third area includes a third element selected from Zr, Y, Ce, Hf, Al, Mg, and Nb, O or N, and a metal element selected from Te, Sb, Bi, Ti, and Zn.

A magnetic memory device may include a substrate, an data storage pattern disposed on the substrate, and a lower contact plug between the substrate and the data storage pattern, the lower contact plug may include a lower insulating pattern, a lower contact pattern on the lower insulating pattern, and a lower barrier pattern extending along a lower surface and a side surface of the lower insulating pattern and a side surface of the lower contact pattern.