In an embodiment, a system includes an energy source and an integrated circuit that is coupled to one or more memory devices via a plurality of memory channels. A memory controller in the integrated circuit is programmable with a plurality of identifiers corresponding to the plurality of channels, and is further programmable with a command and a first identifier associated with the command. Responsive to the command, the memory controller is configured to perform one or more calibrations on a subset of the plurality of channels for which corresponding identifiers of the plurality of identifiers match the first identifier. Other ones of the plurality of channels, for which the corresponding identifiers do not match the first identifier, do not perform the calibration.

Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. In certain examples, the first plurality of pages does not include data from the second data lane.

Stitched dies having a cooling structure are described. For example, an integrated circuit structure includes a first die including a first device layer and a first plurality of metallization layers over the first device layer. The integrated circuit structure also includes a second die including a second device layer and a second plurality of metallization layers over the second device layer, the second die separated from the second die by a scribe region. A common conductive interconnection is coupling the first die and the second die at a first side of the first and second dies. A plurality of microfluidic channels is coupled to the first side of the first and second dies.

Methods, systems, and devices for inductive energy harvesting and signal development for a memory device are described. One or more inductors may be included in or coupled with a memory device and used to provide current for various operations of the memory device based on energy harvested by the inductors. An inductor may harvest energy based on current being routed through the inductor or based on being inductively coupled with a second inductor through which current is routed. After harvesting energy, an inductor may provide current, and the current provided by the inductor may be used to drive access lines or otherwise as part of executing one or more operations at the memory device. Such techniques may improve energy efficiency or improve the drive strength of signals for the memory device, among other benefits.

A power supply switch apparatus includes a first interface, a switch circuit, and a power supply circuit. The first interface includes a first control signal output terminal, a second control signal output terminal, and a third control signal output terminal. Each of the first control signal output terminal, the second control signal output terminal, and the third control signal output terminal outputs a control signal according to an electronic device inserted in the first interface. The switch circuit receives the control signals and outputs a power supply signal accordingly. The power supply circuit receives the power supply signal, and provides a first direct current (DC) voltage or a second DC voltage to the electronic device according to the power supply signal.

A storage device includes a main system; a power loss protection integrated circuit (PLP IC) configured to provide output power to the main system based on external or internal power; and an auxiliary power supply configured to provide the internal power to the PLP IC. The main system may operate in a dump mode where data is backed up in response to at least one of a first condition or a second condition being satisfied. The PLP IC may provide the output power based on the internal power in response to a sudden power off (SPO) occurring. The first condition is satisfied when the SPO occurs and an SPO time is longer than a maximum filtering time. The second condition is satisfied when the SPO occurs and a voltage level of the internal power provided by the auxiliary power supply is lower than a voltage level of a threshold voltage.

Various embodiments described herein use a set of capacitor sets (e.g., capacitor banks) in a power backup architecture for a memory sub-system, where each capacitor set can be individually checked for a health condition (e.g., in parallel) to determine their respective health after the memory sub-system has completed a boot process. In response to determining that at least one capacitor set has failed the health condition (or a certain number of capacitor sets have failed the health condition), the memory sub-system can perform certain operations prior to primary power loss to the memory sub-system (e.g., preemptively performs a data backup process to ensure data integrity) and can adjust the operational mode of the memory sub-system (e.g., switch it from read-write mode to read-only mode).

Disclosed are devices and methods for periodically powering up a storage device(s) (SSDs) associated with a vehicle to avoid and prevent data loss. The disclosed embodiments provide mechanisms for preserving stored data collected during the running of a vehicle without requiring the main power supply to be routed through the CPU. Through the improved configuration and application of the disclosed power management integrated circuitry (PMIC), storage devices of a vehicle are enabled to be provided direct power and refreshed without powering on the vehicle (e.g., starting the car). The PMIC also ensures that the necessary power can be provided to and maintained to the storage device(s) in the event of an unexpected power loss.

A memory subsystem is disclosed comprising at least one memory module, the memory module having a substrate to which a plurality of memory chips is mounted and a voltage regulator, the voltage regulator receiving a power supply signal from a system power supply and outputting two or more power signals, each power signal providing a different, regulated voltage, which regulated voltages are each routed to each of the memory chips; and a redundant voltage regulator external to and not mounted on the memory module and configured to output two or more power signals, providing external different, regulated voltages which are the same voltages as the voltages output by the voltage regulator on the memory module, and supplying the two or more signals to the memory module.

A power supply circuit supplies a first voltage to a third terminal using a voltage of a first terminal, generates a second voltage using the first voltage, supplies the second voltage to a non-volatile memory, generates a third voltage using the first voltage, charges energy in a capacitor, upon the voltage of the first terminal being lower than a first threshold voltage and a voltage of the second terminal being higher than a second threshold voltage, supplies a fourth voltage using charged energy to the third terminal, and upon the voltage of the second terminal being lower than the second threshold voltage, stops charging and supplies a fifth voltage using the charged energy to the third terminal.