A semiconductor device includes a first pad, a comparison circuit, and a control circuit. A first voltage may be applicable to the first pad. The comparison circuit may include a first input terminal connected to the first pad, a second input terminal to which a second voltage is applicable, and an output terminal configured to output a comparison result between the first voltage and the second voltage. The control circuit may be configured to output, external to the semiconductor device, a signal based on the comparison result.

The present application discloses a semiconductor chip, an electronic device and an electrostatic discharge (ESD) protection method for an electronic device thereof. The semiconductor chip includes an operation electrical contact, a detection electrical contact, an ESD protection unit, and a logic circuit. The operation electrical contact receives an operation signal. The detection electrical contact receives a chip connection signal. The ESD protection unit is coupled to the operation electrical contact. The logic circuit is coupled to the detection electrical contact, and adjusts capacitance of the ESD protection unit according to a chip connection signal received by the detection electrical contact.

A power supply circuit of a semiconductor device includes a voltage generation circuit, first and second terminals, and a switch circuit. The voltage generation circuit is configured to generate an operation voltage of the semiconductor device. The first terminal is configured to be at a reference voltage corresponding to an external power supply voltage that is supplied from an external source external to the semiconductor device. The second terminal is connectable to a measuring device. The switch circuit is configured to cause one of the operation voltage and the reference voltage to be output toward the second terminal and then the other of the operation voltage and the reference voltage to be output toward the second terminal.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.

According to one embodiment, a memory system includes a controller controls writing data to a non-volatile memory and a volatile memory, a power supply circuit generates voltages with a first voltage externally supplied and supplies the voltages to the non-volatile memory, volatile memory, and controller, and a backup power supply circuit. The power supply circuit, when the first voltage drops irrespective of a shutdown command, generates the voltages with an output voltage of the backup power supply circuit. The controller changes a size of data storable in the volatile memory in accordance with a supply capability fed from the backup power supply circuit.

Methods, systems, and devices for varying a time average for feedback of a memory system are described. An apparatus may include a voltage supply, a memory array, and a regulator coupled with the voltage supply and memory array and configured to supply a first voltage received from the voltage supply to the memory array. The apparatus may also include a voltage sensor configured to measure a second voltage of the memory array and a digital feedback circuit coupled with the memory array and regulator and configured to generate feedback comprising information averaged over a duration based at least in part on the second voltage measured by the voltage sensor and to transmit an analog signal to the regulator based at least in part on the feedback.

Provided herein is a memory device and a method of operating the memory device. The memory device includes: a reference voltage generation circuit configured to generate a standby mode reference voltage in a standby mode, and generate and output an active mode reference voltage in an active mode; and an internal voltage generation circuit configured to receive the standby mode reference voltage or the active mode reference voltage from the reference voltage generation circuit, and generate an internal voltage. When an error is detected from the internal voltage generated in the standby mode, the reference voltage generation circuit may generate and output the active mode reference voltage.

A memory system includes a nonvolatile memory, a controller configured to control the nonvolatile memory, a power supply circuit that is connected to the controller and configured to generate a power supply voltage for the nonvolatile memory and the controller from a voltage supplied from at least one external power supply, and a power storage device that is connected to the power supply circuit and configured to charge to a first energy from a charging voltage supplied by the power supply circuit, and an energy sharing pin that is connected to the power supply circuit and the power storage device, and is connectable to an external power storage device in an external memory system.

A memory device includes a first memory group including plural first non-volatile memory cells capable of storing multi-bit data, and a second memory group including plural second non-volatile memory cells capable of storing single-bit data. A program operation controller builds the multi-bit data based on data inputted from an external device, performs a logical operation regarding partial data among the multi-bit data to generate a parity, programs the parity in the second memory group after programming the partial data in the first memory group, perform a verification operation regarding the partial data after a sudden power-off (SPO) occurs, recovers the partial data based on the parity and a result of the verification operation, and programs recovered partial data in the first memory group.

An open-channel storage device being configured to be controlled by a host including a bad block manager, the open-channel storage device including a buffer memory and a nonvolatile memory device. An operation method of the open-channel storage device includes performing a normal operation under control of the host, detecting a sudden power-off immediately after a program failure associated with a first data block among a plurality of memory blocks included in the nonvolatile memory device while the normal operation is performed, dumping a plurality of user data stored in the buffer memory to a dump block among the plurality of memory blocks in response to the detected sudden power-off, detecting a power-on, and performing a data recovery operation on the plurality of user data stored in the dump block in response to the detected power-on.