A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.

An electronic device and a semiconductor package structure are provided. The device includes a plurality of semiconductor dies stacked vertically over each other and a power supply system. The semiconductor dies are stacked over the power supply system. The power supply system includes: a voltage generating circuit configured to generate at least one voltage. The at least one voltage is provided to the plurality of semiconductor dies through a power interconnecting structure. The semiconductor package structure includes a package substrate; at least one semiconductor die disposed on the package substrate; and the power supply system disposed on the package substrate. The at least one semiconductor die may include a plurality of semiconductor dies vertically stacked on the package substrate.

A method of operating a memory device comprises generating a target voltage using a pump circuit of the memory device, the target voltage to be applied to a word line or pillar of a memory cell of the memory device; providing an indication of current generated by the pump circuit after the pump circuit output reaches the target voltage; and determining when the current generated by the pump circuit is greater than a specified threshold current and generating a fault indication according to the determination.

A voltage regulator receives an input voltage and produces a regulated output voltage. A first feedback network compares a feedback signal to a reference signal to assert/de-assert a first pulsed control signal when the reference signal is higher/lower than the feedback signal. A second feedback network compares the output voltage to a threshold signal to assert/de-assert a second control signal when the threshold signal is higher/lower than the output voltage. A charge pump is enabled if the second control signal is de-asserted and is clocked by the first pulsed control signal to produce a supply voltage higher than the input voltage. A first pass element is enabled when the second control signal is asserted and is selectively activated when the first pulsed control signal is asserted. A second pass element is selectively activated when the second control signal is de-asserted.

A memory device, can include: a control circuit configured to operate the memory device in one of an active mode, a standby mode, and a sleep mode, where the memory device is configured to receive a command from a host device when in the standby mode; a voltage regulator having an output that provides a supply voltage for accessing contents of memory cells in the memory device, where the voltage regulator is off during the sleep mode and the standby mode, and the voltage regulator is on during the active mode; and a storage element configured to maintain the supply voltage to allow the voltage regulator to be turned off during the standby mode, and at least until the voltage regulator turns on in the active mode and supports the supply voltage.

Apparatuses and methods related to memory disablement for memory security. Disabling the memory for memory security can include, responsive to receiving a trigger signal, provide a voltage, which may be in excess of an operating or nominal voltage, to the access circuitry. The voltage may thus be sufficient to render the access circuitry inoperable for accessing data stored in the memory array.

A memory device includes a charge pump connected to a power supply voltage and including a plurality of stages to output an output voltage, a stage counter configured to output a count value that incrementally increases to a number of the stages, and a regulator configured to compare the output voltage with a reference output voltage of the charge pump that is generated using the incrementally increasing count value obtained by the stage counter, and to output a pump operation signal at a time when the reference output voltage becomes greater than or equal to the output voltage, wherein the charge pump operates in response to the pump operation signal.

A storage device includes: a controller that exchanges data with a host through an interface; memory devices that store the data; a power supply circuit that outputs internal voltages, required for the controller and the memory devices, using an external voltage received through the interface; a distribution circuit that provides an operating voltage to the memory devices; and a discharge circuit including a first comparator that compares a first internal voltage, among the internal voltages, with a reference voltage and a second comparator that compares a second internal voltage, different from the first internal voltage, with the reference voltage, and including an operating circuit that computes an output of the first comparator and an output of the second comparator to output a discharge control signal determining whether the operating voltage has been discharged.

A semiconductor storage device includes a first memory chip having a first memory cell, a first word line connected to the first memory cell, a first voltage step-up circuit, and a second voltage step-up circuit, and a second memory chip having a second memory cell, a second word line connected to the second memory cell, a third voltage step-up circuit, and a fourth voltage step-up circuit. During a read operation executed in the first memory chip, the first, second, and fourth voltage step-up circuits supply a first voltage to the first word line, and when a voltage of the first word line reaches a predetermined voltage, the first voltage step-up circuit continues to supply the first voltage to the first word line, and the second voltage step-up circuit and the fourth voltage step-up circuit stop supplying the first voltage to the first word line.

A pumping capacitor is provided. The pumping capacitor includes: first, second, third and fourth electrodes that are separately formed on a substrate; a first pumping capacitor group, wherein i first cell capacitors have lower electrodes formed on the first pad electrode and upper electrodes connected to a plate electrode, and (n−i) first cell capacitors have lower electrodes formed on the second pad electrode and upper electrodes connected to the plate electrode; and a second pumping capacitor group, wherein i second cell capacitors have lower electrodes formed on the fourth pad electrode and upper electrodes connected to the plate electrode, and (n−i) second cell capacitors have lower electrodes formed on the third pad electrode and upper electrodes connected to the plate electrode. The first pumping capacitor group and the second pumping capacitor group are connected in series, and the second pad electrode and the third pad electrode are floated.