Disclosed is a low dropout regulator which includes a first resistor, a first transistor including a gate terminal connected with a first end of the first resistor, a source terminal connected with a power supply voltage terminal, and a drain terminal connected with a first node, an operational amplifier including input terminals respectively connected with a reference voltage and the first node and an output terminal, a second transistor including a gate terminal connected with the output terminal of the operational amplifier, a source terminal connected with the first node, and a drain terminal connected with a second node, a third transistor including a gate terminal connected with a second end of the first resistor, a source terminal connected with the power supply voltage terminal, and a drain terminal connected with a third node, and a current source connected between the second node and a ground voltage terminal.

A dual-rail memory includes, in part, a memory array that operates using a first supply voltage, and a periphery circuit that operates using a second supply voltage. The periphery circuit includes, in part, a clock generation circuit and a comparator. The dual-rail memory also includes a level shifter that varies the voltage level of a number of signals of the memory between the first and second supply voltages. The clock generation circuit is adapted, among other operations, to generate a read clock signal in response to a read request signal. The level shifter is adapted to supply a reference wordline read signal in response to the read clock signal. The comparator is adapted to select a delay between the read clock signal and the reference wordline read signal in response to a difference between the first and second supply voltages.

The present disclosure describes a power supply switch that includes a voltage generator, a switch circuit, and a confirmation circuit. The voltage generator is configured to compare a first power supply voltage to a second power supply voltage and to output the first power supply voltage or the second power supply voltage as a bulk voltage (V.sub.bulk). The switch circuit includes one or more transistors and is configured to (i) bias bulk terminals of the one or more transistors with the V.sub.bulk and (ii) output either the first power supply voltage or the second power supply voltage as a voltage output signal. The confirmation circuit is configured to output a confirmation signal that indicates whether the voltage output signal transitioned from the first power supply voltage to the second power supply voltage.

Provided is a semiconductor package. The semiconductor package comprises a semiconductor chip on a substrate, a voltage measurement circuit configured to measure an external voltage to be input into the semiconductor chip and a thermoelectric module configured to convert heat released from the semiconductor chip into an auxiliary power, and configured to apply the auxiliary power to the semiconductor chip, the thermoelectric module being separated from the voltage measurement circuit, wherein the voltage measurement circuit is configured to control the thermoelectric module to apply the auxiliary power to the semiconductor chip in response to a change in the external voltage.

In one embodiment, a programming circuit is configured to form a programming current for a silicide fuse element by using a non-silicide programming element.

A system for dual mode operation having power saving and active modes in a stacked circuit topology having logic preservation is provided. The system includes a pre-charge circuit and a sleep mode control circuit for providing a signal to disable a plurality of circuit elements and switching a mode of the system, the sleep mode control circuit being coupled to the pre-charge circuit and further being coupled to a logic function circuit, wherein the plurality of circuit elements comprise logic gates and transistor devices. The system also includes a keeper circuit coupled to the global bitline, and the logic function circuit coupled to a solar bitline, wherein the logic function circuit preserves a state of the solar bitline, the state of the global bitline determines the state of the solar bitline. The system includes an effective pull-up transistor coupled to the sleep mode control circuit and the logic function circuit.

A voltage selection circuit, including: first and second nodes of application of first and second input voltages; a third output voltage supply node; first and second MOS transistors respectively coupling the first and third nodes and the second and third nodes; and a control circuit capable of keeping the first and second transistors either respectively on and off or respectively off and on, the control circuit including a feedback loop from the third node to the gate of the first transistor and being capable, during a transition phase, of controlling the first transistor in linear operating region to apply a DC voltage ramp to the third node.

A method of peak power management (PPM) is provided for two NAND memory dies. each NAND memory die comprises a PPM circuit having a PPM contact pad held at an electric potential common between the two NAND memory dies. The method includes the following steps: detecting the electric potential during a first peak power check (PPC) routine for the first NAND memory die; driving the electric potential to a second voltage level if the detected electric potential is at a first voltage level higher than the second voltage level; generating a pausing signal in the electric potential to pause a second PPC routine for the second NAND memory die if no pausing signal is detected; and generating a resuming signal in the electric potential to resume the second PPC routine for the second NAND memory die after the first NAND memory die completes a first peak power operation.

Methods, systems, and devices for power regulation for memory systems are described. In one example, a memory system, such as a memory module, may include a substrate, and an input/output component coupled with the substrate and operable to communicate signals with a host system. The memory system may also include one or more memory devices coupled with the substrate and the input/output component and operable to store data for the host system. A memory device of the one or more memory devices may include a power management component in its package with one or more memory dies. The power management component may be coupled with the one or more memory dies, and feedback component, and may be operable to provide one or more supply voltages for the one or more memory dies based on one or more voltages associated with the memory system.

Methods of forming a capacitor structure might include forming a first and second conductive regions having first and second conductivity types, respectively, in a semiconductor material, forming a dielectric overlying the first and second conductive regions, forming a conductor overlying the dielectric, and patterning the conductor, the dielectric, and the first and second conductive regions to form a first island of the first conductive region, a second island of the first conductive region, an island of the second conductive region, a first portion of the dielectric overlying the first island of the first conductive region separated from a second portion of the dielectric overlying the second island of the first conductive region and the island of the second conductive region, and a first portion of the conductor overlying the first portion of the dielectric separated from a second portion of the conductor overlying the second portion of the dielectric.