A sub-sense amplifier includes a semiconductor substrate, a first pair of complementary transistors, a second pair of complementary transistors, and at least one ground transistor. The first pair and second pair of complementary transistors and the ground transistor are formed on the semiconductor substrate. The first pair of complementary transistors are disposed in line symmetry with a center line of the sub-sense amplifier as a symmetry axis, and gates of the first pair of complementary transistors are coupled to a node. The second pair of complementary transistors are also disposed in line symmetry with the center line, wherein the current directions of the second pair of complementary transistors are the same. Sources and drains of the first pair of complementary transistors are coupled to gates and sources of the second pair of complementary transistors, respectively. The ground transistor connects in series with the second pair of complementary transistors.

A semiconductor storage device includes a memory cell including a switching element and a variable resistance element, and a circuit for switching the memory cell ON, performing a first read operation on the memory cell, generating a first voltage based on the first read operation, switching the memory cell ON after first data is written to the memory cell, performing a second read operation while the memory cell is maintained to be ON when the first data is stored in the memory cell during the first read operation, performing the second read operation after the memory cell transitions from ON to OFF at least once when second data is stored in the memory cell during the first read operation, generating a second voltage based on the second read operation, and determining the data stored in the memory cell during the first read operation based on the first and second voltages.

Electrically conductive line side-by-side running distance equalization and related apparatuses and systems. An apparatus includes a first sense amplifier, a second sense amplifier, a first pair of lines, and a second pair of lines. The first sense amplifier includes a first pull-up sense amplifier and a first pull-down sense amplifier. The first pair of lines electrically connects a first pull-up sense amplifier of the first sense amplifier to a first pull-down sense amplifier of the first sense amplifier. The second pair of lines electrically connects the second pull-up sense amplifier to the second pull-down sense amplifier. Parallel running distances between lines of the first pair of lines and the second pair of lines are equalized by a wiring twist of the first pair of lines and three wiring twists of the second pair of lines.

Methods, systems, and devices for operating a memory device are described. One method includes caching data of a memory cell at a sense amplifier of a row buffer upon performing a first read of the memory cell; determining to perform at least a second read of the memory cell after performing the first read of the memory cell; and reading the data of the memory cell from the sense amplifier for at least the second read of the memory cell.

A comparison circuit includes a comparison module, a state judgment module and a state storage module. The comparison module includes a first input end connected to a voltage to be measured and a second input end connected to a reference voltage. The state judgment module includes a first input end connected to a first output end of the comparison module and a second input end connected to a second output end of the comparison module. The state storage module includes an input end connected to the first output end of the comparison module and an enable end connected to an output end of the state judgment module. The embodiments of the disclosure may improve processing efficiency of the comparison circuit.

A memory device comprising a plurality of memory cells situated in a first cell field, multiple first bit lines, each respectively connected to multiple memory cells of the first cell field to enable access to the memory cells via the bit line, and multiple sense amplifier pairs which respectively comprise a first and a second sense amplifier. Each first bit line is assigned to a sense amplifier pair, each first bit line being connected to a respective first semiconductor switch element, through which the bit line is electroconductively connectible to and insulatable from the first sense amplifier of the sense amplifier pair, to which the bit line is assigned. Each first bit line is connected to a respective second semiconductor switch element, through which the bit line is electroconductively connectible to and insulatable from the second sense amplifier of the sense amplifier pair, to which the bit line is assigned.

Embodiments of the present application provide a readout circuit layout structure, a readout circuit, and a memory layout structure. The readout circuit layout structure includes: a readout amplification module, a first processing module, and a second processing module arranged along a preset direction, wherein the readout amplification module is configured to read a voltage of a bit line, and the first processing module and the second processing module are at least configured to perform a noise cancellation on an output signal of the readout amplification module. The readout amplification module includes: a first NMOS region and a first PMOS region arranged close to the first processing module, and a second NMOS region and a second PMOS region arranged close to the second processing module, the first NMOS region, the first PMOS region, the second PMOS region, and the second NMOS region being arranged along the preset direction.

A storage device includes a storage circuit, a reading circuit, a first check circuit, and a second check circuit. The storage circuit includes a plurality of sense amplifier arrays and a plurality of storage unit arrays which are arranged alternately. A first data wire is electrically connected to each of the sense amplifier arrays. The reading circuit is configured to read data on the first data wire. Both the first check circuit and the second check circuit are electrically connected to the reading circuit. The reading circuit is configured to transmit a part of the read data to the first check circuit for error checking and/or correcting, and transmit another part of the read data to the second check circuit for error checking and/or correcting. The data transmitted to the first check circuit and the data transmitted to the second check circuit are respectively from adjacent sense amplifier arrays.

A memory includes a storage circuit, a first reading circuit, a second reading circuit, and a plurality of correcting circuits. The storage circuit includes a plurality of sense amplifier arrays and a plurality of storage unit arrays. The sense amplifier arrays and the storage unit arrays are arranged alternately, and the sense amplifier arrays are configured to perform data reading and writing on the storage unit arrays. The first reading circuit is configured to compare a reference voltage signal with a signal on a first data line corresponding to the first reading circuit, and output a comparison result as read-out data. The second reading circuit is configured to compare the reference voltage signal with a signal on a first data line corresponding to the second reading circuit, and output a comparison result as read-out data.

An electronic device and method of generating a Physically Unclonable Function (“PUF”) value is disclosed. An OTP memory with a plurality of OTP cells that can be reliably and deterministically programmed with a minimum and a maximum program voltage being selected for pre-conditioning. All OTP cells can be programmed at least once around the minimum program voltage to hide the program status. Data to be programmed into the OTP can be a fixed, time-varying voltage or data from an entropy source. The programmed OTP data can be masked for weak bits and further randomized to generate PUF output by compressing a bit stream into a single bit, e.g., single parity bit. The PUF output can be through a hash function and/or to generate keys.