A sensing device for a non-volatile memory includes a reference circuit, two switches, a sensing circuit and a judging circuit. The reference circuit is connected to a first node. A first terminal of the first switch is connected with the first node and a control terminal of the first switch receives an inverted reset pulse. A first terminal of the second switch is connected with the first node, a second terminal of the second switch receives a ground voltage, and a control terminal of the second switch receives a reset pulse. The sensing circuit is connected between the second terminal of the first switch and a second node. The sensing circuit generates a first sensed current. The judging circuit is connected to the second node. The judging circuit receives the first sensed current and generates an output data according to the first sensed current.

The present disclosure relates to semiconductor structures and, more particularly, to sensing circuit for a memory and methods of use. The memory includes a self-referenced sense amp that is structured to calibrate its individual pre-charge based on a trip-point, with autonomous pre-charge activation circuitry that starts pre-charging a sense-line on each unique entry as soon as a sense has been performed or completed.

Technology is disclosed herein for testing circuitry that controls memory operations in a memory structure having non-volatile memory cells. The testing of the circuitry can be performed without the memory structure. The memory structure may reside on one semiconductor die, with sense blocks and a control circuit on another semiconductor die. The control circuit is able to perform die level control of memory operations in the memory structure. The control circuit may control the sense blocks to simulate sensing of non-volatile memory cells in the memory structure even though the sense blocks are not connected to the memory structure. The control circuit verifies correct operation of the semiconductor die based on the simulated sensing. For example, the control circuit may verify correct operation of a state machine that controls sense operations at a die level. Thus, the operation of the semiconductor die may be tested without the memory structure.

Methods for precharging bit lines using closed-loop feedback are described. In one embodiment, a sense amplifier may include a bit line precharge circuit for setting a bit line to a read voltage prior to sensing a memory cell connected to the bit line. The bit line precharge circuit may include a first transistor in a source-follower configuration with a first gate and a first source node electrically coupled to the bit line. By applying local feedback from the first source node to the first gate, the bit line settling time may be reduced. In some cases, a first voltage applied to the first gate may be determined based on a first current drawn from the first bit line. Thus, the first voltage applied to the first gate may vary over time depending on the conductivity of a selected memory cell connected to the bit line.

An electronic device includes a semiconductor memory unit. The semiconductor memory unit may include a cell array suitable for including a plurality of resistive memory cells which are arranged in a plurality of column lines and a plurality of rows lines, and a read circuit. The read circuit is suitable for, in a read operation, generating a bias current based on bias information, supplying the bias current to a sensing node, supplying a read current from the sensing node to a column line selected from among the plurality of column lines, and sensing data stored in a selected memory cell coupled to the selected column line using a voltage level at the sensing node. The bias information is determined and stored in the semiconductor memory unit before the read operation starts.

A memory device includes a memory cell and a sense amplifier. The sense amplifier has a reference circuit configured to output a reference voltage and a sensing circuit connected to the memory cell. A comparator includes a first input and a second input, with the first input connected to the reference circuit to receive the reference voltage, and the second input connected to the memory cell. A precharger is configured to selectively precharge the sensing circuit to a predetermined precharge voltage

Various implementations provide systems and methods for reading data from memory bit cells. An example implementation includes a read circuit that provides a single-ended output from a sensing stage. The single-ended output is received by a reset-set (RS) latch, which also receives a virtual bit line signal. The single-ended output and the virtual bit line signal provide complementary inputs to the RS latch, and the RS latch stores a sensed bit, and the sensed bit may be driven onto a data bus.

A single-ended sense amplifier and a memory device including the same are presented. A sense amplifier, which senses and amplifies data of a memory cell, may include a precharge circuit pre-charging a data line which is connected to the memory cell and provides a sensing voltage, and a reference line which provides a reference voltage, with a power supply voltage; a reference voltage generating circuit which generates the reference voltage by discharging the reference line based on a reference current, and adjusts an amount of the reference current based on the data of the memory cell; and a comparator which compares the sensing voltage and the reference voltage, and outputs a comparison result as the data of the memory cell.

Disclosed is a memory device, which includes a memory cell, a bit line connected to the memory cell, a controller that generates at least one current control code, a first current generator that generates a first current having a proportional to absolute temperature (PTAT) characteristic, based on the at least one current control code from the controller, a second current generator that generates a second current having a complementary to absolute temperature (CTAT) characteristic, based on the at least one current control code from the controller, a subtractor that generates a third current by subtracting the second current from the first current, and a sense amplifier that controls a load current to be supplied to the bit line based on the third current, and generates a bit line compensation current for compensating for a leakage current of the bit line.

A semiconductor memory apparatus, including a first mat which includes a first bit line and a first word line and a second mat which includes a second bit line and a second word line, includes a first bit line driving circuit configured to enable the first bit line in response to a first bit line select signal and a first machine bit line select signal; a second bit line driving circuit configured to enable the second bit line in response to a second bit line select signal and a second machine bit line select signal; a column-related decoding circuit configured to selectively enable the first and second bit line select signals in response to a column address; and a state machine configured to selectively enable the first and second machine bit line select signals in response to the column address.