A method for obtaining circuit noise parameters and an electronic device are provided. The method includes: determining a plurality of circuits to be tested, where each circuit includes one or more signal lines, and each circuit has at least one operating state; obtaining a parasitic capacitance between each signal line and all others signal lines, and determining a logic state of each signal line under each of the operating states; determining a plurality of operating state combinations for the plurality of circuits to be tested, and determining one target operating state combination from the plurality of operating state combinations; and under the target operating state combination, determining noise parameters of each one of the signal lines to be tested according to the logic state of each one of the signal lines to be tested and the parasitic capacitance.

A method for obtaining circuit noise parameters and an electronic device are provided. The method includes: determining a plurality of circuits to be tested, where each circuit includes one or more signal lines, and each circuit has at least one operating state; obtaining a parasitic capacitance between each signal line and all others signal lines, and determining a logic state of each signal line under each of the operating states; determining a plurality of operating state combinations for the plurality of circuits to be tested, and determining one target operating state combination from the plurality of operating state combinations; and under the target operating state combination, determining noise parameters of each one of the signal lines to be tested according to the logic state of each one of the signal lines to be tested and the parasitic capacitance.

A system is provided. The system includes a multiply-and-accumulate circuit and a local generator. The multiply-and-accumulate circuit is coupled to a memory array and generates a multiply-and-accumulate signal indicating a computational output of the memory array. The local generator is coupled to the memory array and generates at least one reference signal at a node in response to one of a plurality of global signals that are generated according to a number of the computational output. The local generator is further configured to generate an output signal according to the signal and a summation of the at least one reference signal at the node.

The present invention includes apparatus and a method for reading one or more data states from an integrated circuitry memory cell, including the steps of connecting the memory cell to a bit line which is connected to an amplifier having an offset control which introduces an offset during the sensing portion of a read cycle to identify a data state stored in the memory cell.

A memory device that operates at high speed is provided. The memory device includes first and second memory cells, first and second bit lines, first and second switches, and a sense amplifier. The sense amplifier comprises a first node and a second node. The first memory cell is electrically connected to the first node through the first bit line and the first switch, and the second memory cell is electrically connected to the second node through the second bit line and the second switch. The sense amplifier amplifies the potential difference between the first node and the second node. The first memory cell and the second memory cell include an oxide semiconductor in a channel formation region.

Embodiments relate to improving the biasing of active electronic components such as, for example, sense amplifiers. Embodiments include an adjustable bias signal generator that receives a reference signal as an input and generates a corresponding bias signal as an output. The adjustable bias signal generator may comprise a voltage driver and capacitor divider circuitry. In some embodiments, the capacitor divider circuitry is configurable by selecting specific capacitor dividers using a digital code. In other embodiments, the voltage driver is adjustable by applying different trim settings to tune the output of the voltage driver. The voltage driver may be temperature compensated by multiplexing different trim settings that correspond to different temperatures.

Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.

The present invention includes apparatus and a method for reading one or more data states from an integrated circuitry memory cell, including the steps of connecting the memory cell to a bit line which is connected to an amplifier having an offset control which introduces an offset during the sensing portion of a read cycle to identify a data state stored in the memory cell.

Methods, systems, and devices for configurable input for an amplifier are described. In some examples, a circuit may be configured to operate based on a signal having a first voltage profile or a second voltage profile. For example, the first voltage profile may be associated with a range of voltages that are based on a temperature of an associated memory chip, and the second voltage profile may be associated with a voltage (or voltages) that are not associated with the temperature of the memory chip. The circuit may include one or more transistors and switches that are activated based on the voltage profile and a switch receiving a particular control signal. In some instances, the control signal may be received based on a value stored to one or more non-volatile memory elements.

Methods, systems, and devices related to domain-based access in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory array may be organized according to domains, which may refer to various configurations or collections of access lines, and selections thereof, of different portions of the memory array. In various examples, a memory device may determine a plurality of domains for a received access command, or an order for accessing a plurality of domains for a received access command, or combinations thereof, based on an availability of the signal development cache.