The present disclosure includes apparatuses and methods related to memory module interfaces. A memory module, which may include volatile memory or nonvolatile memory, or both, may be configured to communicate with a host device via one interface and to communicate with another memory module using a different interface. Memory modules may thus be added or removed from a system without impacting a PCB-based bus to the host, and memory modules may communicate with one another without accessing a bus to the host. The host interface may be configured according to one protocol or standard, and other interfaces between memory modules may be configured according to other protocols or standards.

A storage device includes a memory controller and a plurality of memory devices. The plurality of memory devices comprise a first memory device coupled to the memory controller and an n.sup.th memory device coupled in series to the first memory device, where n is a natural number greater than 1. The memory controller is configured to transmit, to a first memory device, a signal that includes a target ID indicating a selected memory device from among the plurality of memory devices. Each memory device includes a plurality of memory dies, an interface configured to distribute the signal based on the target ID, and a redriver configured to redrive the signal such that the signal is transferred to another memory device.

Flexible command addressing for memory. An embodiment of a memory device includes a dynamic random-access memory (DRAM); and a system element coupled with the DRAM, the system element including a memory controller for control of the DRAM. The DRAM includes a memory bank, a bus, the bus including a plurality of pins for the receipt of commands, and a logic, wherein the logic provides for shared operation of the bus for a first type of command and a second type of command received on a first set of pins.

A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.

A semiconductor memory device includes a memory cell array and a control logic circuit. The control logic circuit controls access to the memory cell array based on a command and an address. The semiconductor memory device performs a write operation to write data in the memory cell array and performs a read operation to read data from the memory cell array in synchronization with a clock signal from an external memory controller. The semiconductor memory device performs the write operation and the read operation in different data strobe modes in which the semiconductor memory device uses different numbers of data strobe signals according to a frequency of the clock signal.

A storage device includes a controller including first and second pins and configured to output a multi-level chip enable signal through the second pin, and a memory device. The memory device includes third and fourth pins respectively connected to the first and second pins, and a plurality of memory chips commonly connected to the fourth pin. The plurality of memory chips respectively include a plurality of resistors connected to one another in a daisy-chain structure between the third pin and a first voltage terminal. The plurality of memory chips are configured to respectively generate a plurality of reference voltage periods that divide between a voltage level of the third pin and a voltage level of the first voltage terminal based on the plurality of resistors.

A stacked memory device includes memory dies over a base die. The base die includes separate memory channels to the different dies and external channels that allow an external processor access to the memory channels. The base die allows the external processor to access multiple memory channels using more than one external channel. The base die also allows the external processor to communicate through the memory device via the external channels, bypassing the memory channels internal to the device. This bypass functionality allows the external processor to connect to additional stacked memory devices.

A method for providing a datum in a receive buffer memory. The method includes storing the datum to be provided in the receive buffer memory, and retrieving an old datum from the receive buffer memory, if the receive buffer memory overflows as a result of storing the datum to be provided.

An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.

The disclosed multi-level driving data transmission circuit and operating method include: a first driving module including a first signal generating unit and a first three-state driver, and a second driving module, including a second three-state driver. The first input terminal of the second three-state driver is coupled to the output terminal of the first three-state driver. The first signal generating unit includes a first and second input terminals, and an output terminal. The output terminal of the first signal generating unit couples to the second input terminal of the first three-state driver. The first signal generating unit receives the first signal through its first input terminal and the first feedback signal of the first signal from the second driving module through its second input terminal. The resultant first control signal has an effective signal width wider than the first signal. The first control signal inputs to the first three-state driver.