Aspects of the present disclosure are directed to devices and methods for performing MAC operations using a memory array as a compute-in-memory (CIM) device that can enable higher computational throughput, higher performance and lower energy consumption compared to computation using a processor outside of a memory array. In some embodiments, an activation architecture is provided using a bit cell array arranged in rows and columns to store charges that represent a weight value in a weight matrix. A read word line (RWL) may be repurposed to provide the input activation value to bit cells within a row of bit cells, while a read-bit line (RBL) is configured to receive multiplication products from bit cells arranged in a column. Some embodiments provide multiple sub-arrays or tiles of bit cell arrays.

A device includes a multiplication unit and a configurable summing unit. The multiplication unit is configured to receive data and weights for an Nth layer, where N is a positive integer. The multiplication unit is configured to multiply the data by the weights to provide multiplication results. The configurable summing unit is configured by Nth layer values to receive an Nth layer number of inputs and perform an Nth layer number of additions, and to sum the multiplication results and provide a configurable summing unit output.

A memory device including a memory array configured to store data, a sense amplifier circuit coupled to the memory array, and a read circuit coupled to the sense amplifier circuit, wherein the read circuit includes a first input that receives a read column select signal for activating the read circuit to read the data out of the memory array through the read circuit during a read operation.

A memory device for data searching and a data searching method thereof are provided. The data searching method includes the following steps. A searching word is received and then divided into a plurality of sections. The sections are encoded as a plurality of encoded sections, so that the encoded sections may correspond to a plurality of memory blocks in a memory array. The encoded sections are directed into the memory blocks to perform data comparisons and obtaining a respective result of data comparison. Thereafter, addresses of bit lines which match the searching word are obtained according to respective result of data comparison for each of memory block.

An in-memory computing system for computing vector-matrix multiplications includes an array of resistive memory devices arranged in columns and rows, such that resistive memory devices in each row of the array are interconnected by a respective word line and resistive memory devices in each column of the array are interconnected by a respective bitline. The in-memory computing system also includes an interface circuit electrically coupled to each bitline of the array of resistive memory devices and computes the vector-matrix multiplication between an input vector applied to a given set of word lines and data values stored in the array. For each bitline, the interface circuit receives an output in response to the input being applied to the given wordline, compares the output to a threshold, and increments a count maintained for each bitline when the output exceeds the threshold. The count for a given bitline represents a dot-product.

An apparatus includes first and second compute-in-memory (CIM) arrays. The first CIM array is configured to store weights corresponding to a filter tensor, to receive a first set of activations corresponding to a first receptive field of an input, and to process the first set of activations with the weights to generate a corresponding first tensor of output values. The second CIM array is configured to store a first copy of the weights corresponding to the filter tensor and to receive a second set of activations corresponding to a second receptive field of the input. The second CIM array is also configured to process the second set of activations with the first copy of the weights to generate a corresponding second tensor of output values. The first and second compute-in-memory arrays are configured to process the first and second receptive fields in parallel.

Systems, methods and apparatus to determine a programming mode of a set of memory cells that store an indicator of the programming mode. In response to a command to read the memory cells in a memory device, a first read voltage is applied to the memory cells to identify a first subset of the memory cells that become conductive under the first read voltage. The determination of the first subset is configured as an operation common to different programming modes. Based on whether the first subset of the memory cell includes one or more predefined memory cells, the memory device determines a programming mode of memory cells. Once the programming mode is identified from the common operation, the memory device can further execute the command to determine a data item stored, via the programming mode, in the memory cells.

Embodiments of the present invention provides a system and method of learning and classifying features to identify objects in images using a temporally coded deep spiking neural network, a classifying method by using a reconfigurable spiking neural network device or software comprising configuration logic, a plurality of reconfigurable spiking neurons and a second plurality of synapses. The spiking neural network device or software further comprises a plurality of user-selectable convolution and pooling engines. Each fully connected and convolution engine is capable of learning features, thus producing a plurality of feature map layers corresponding to a plurality of regions respectively, each of the convolution engines being used for obtaining a response of a neuron in the corresponding region. The neurons are modeled as Integrate and Fire neurons with a non-linear time constant, forming individual integrating threshold units with a spike output, eliminating the need for multiplication and addition of floating-point numbers.

The present disclosure relates to devices and methods for using a banked memory structure with accelerators. The devices and methods may segment and isolate dataflows in datapath and memory of the accelerator. The devices and methods may provide each data channel with its own register memory bank. The devices and methods may use a memory address decoder to place the local variables in the proper memory bank.

Systems, apparatuses and methods include technology that identifies whether a product of first and second digital numbers is associated with a positive value or a negative value. During a first clock phase, the technology sets a first reference voltage to have a first value or a second value based on whether the product is associated with the positive value or the negative value. During the first clock phase, the technology controls switches to supply the first reference voltage to first plates of capacitors. Each of the capacitors includes a respective first plate of the first plates and a second plate. Further, during the first clock phase, the technology controls the switches based on the first digital number to electrically connect at least one of the second plates to the first reference voltage and electrically connect at least one of the second plates to a second reference voltage.