A memory device includes a command interface configured to receive a two-cycle command from a host device via multiple command address bits. The memory device also includes a command decoder configured to decode a first portion of the multiple command address bits in a first cycle of the two-cycle command. The command decoder includes mask circuitry. The mask circuitry includes mask generation circuitry configured to generate a mask signal. The mask circuitry also includes multiplexer circuitry configured to apply the mask signal to block the command decoder from decoding a second portion of the multiple command address bits in a second cycle of the two-cycle command.

The present disclosure discloses a memory access interface device. A clock generation circuit generates a reference clock signal. A fake data strobe signal generation circuit receives the reference clock signal and delays a read enable signal from a memory access controller to enable an output of the reference clock signal to generate a fake data strobe signal. A real data strobe signal generation circuit receives a data strobe signal from a memory device and delays the read enable signal to enable an output of the data strobe signal to generate a real data strobe signal. A data reading circuit samples a data signal from the memory device according to a sampling signal to generate a read data signal to the memory access controller. A selection circuit selects the fake and the real data strobe signals as the sampling signal respectively under a single and a double data rate modes.

Systems, apparatuses, and methods for performing asynchronous memory clock changes on multiple displays are disclosed. From time to time, a memory clock frequency change is desired for a memory subsystem storing frame buffer(s) used to drive pixels to multiple displays. For example, when the real-time memory bandwidth demand differs from the memory bandwidth available with the existing memory clock frequency, a control unit tracks the vertical blanking interval (VBI) timing of a first display. Also, the control unit causes a second display to enter into panel self-refresh (PSR) mode. Once the PSR mode of the second display overlaps with a VBI of the first display, a memory clock frequency change, including memory training, is initiated. After the memory clock frequency change, the displays are driven by the frame buffer(s) in the memory subsystem at an updated frequency.

According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.

Systems and methods for processing commands at a random access memory. A series of commands are received to read data from the random access memory or to write data to the random access memory. The random access memory can process commands at a first rate when the series of commands matches a pattern, and at a second, slower, rate when the series of commands does not match the pattern. A determination is made as to whether the series of commands matches the pattern based on at least a current command and a prior command in the series of commands. A ready signal is asserted when said determining determines that the series of commands matches the pattern, where the random access memory is configured to receive and process commands faster than the second rate when the pattern is matched and the ready signal is asserted over a period of multiple commands.

Technologies for allocating resources of managed nodes to workloads to balance multiple resource allocation objectives include an orchestrator server to receive resource allocation objective data indicative of multiple resource allocation objectives to be satisfied. The orchestrator server is additionally to determine an initial assignment of a set of workloads among the managed nodes and receive telemetry data from the managed nodes. The orchestrator server is further to determine, as a function of the telemetry data and the resource allocation objective data, an adjustment to the assignment of the workloads to increase an achievement of at least one of the resource allocation objectives without decreasing an achievement of another of the resource allocation objectives, and apply the adjustments to the assignments of the workloads among the managed nodes as the workloads are performed. Other embodiments are also described and claimed.

A memory device includes a plurality of data input/output (I/O) groups each including data I/O circuits, each data I/O circuit comprising a transistor having a predetermined threshold voltage according to a bulk voltage supplied to a bulk terminal thereof; a control circuit suitable for generating a control signal according to a data I/O mode; and a plurality of voltage supply circuits suitable for independently supplying bulk voltages to the plurality of data I/O groups, and changing, in response to the control signal, a level of a bulk voltage corresponding to data I/O groups unused in the data I/O mode, among the plurality of data I/O groups.

An electronic circuit includes a memory buffer and control logic. The memory buffer is configured to transfer data from a first domain to a second domain of the circuit, the first and the second domains operate in synchronization with respective clock signals. The control logic is configured to maintain a write indicator in the first domain indicative of a next write position in the memory buffer for storing data, to maintain a read indicator in the second domain indicative of a next read position in the memory buffer for retrieving the stored data, to generate in the second domain, based on the write and the read indicators, a first signal that is indicative of whether the memory buffer has data for reading or has become empty, and retain the first signal in a state that indicates that the memory buffer has become empty, until writing to the memory buffer resumes.

The present invention relates to a bioactive agent capable of increasing the intracellular concentration and/or activity of Hsp70 for use in the treatment of a lysosomal storage disease which arise from a defect in an enzyme whose activity is not directly associated with the presence of lysosomal BMP as a co-factor; such as glycogen storage diseases, gangliosidoses, neuronal ceroid lipofuscinoses, cerebrotendinous cholesterosis, Wolman's disease, cholesteryl ester storage disease, disorders of glycosaminoglycan metabolism, mucopolysaccharidoses, disorders of glycoprotein metabolism, mucolipidoses, aspartylglucosaminuria, fucosidosis, mannosidoses, and sialidosis type II.

Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuitry is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.