An integrated circuit includes a plurality of memory cells, a first pair of complementary data lines, and a second pair of complementary data lines. The plurality of memory cells include a first array of memory cells and a second array of memory cells. The first pair of complementary data lines are coupled to the first array of memory cells. The second pair of complementary data lines are different from the first pair of complementary data lines and are coupled to the second array of memory cells. A number of memory cells in the first array of memory cells is different from a number of memory cells in the second array of memory cells.

A memory controller configured to control a non-volatile memory device includes: a signal generator configured to generate a plurality of control signals comprising a first signal and a second control signal; a core configured to provide a command for an operation of the non-volatile device; and a controller interface circuit configured to interface with the non-volatile memory device, wherein the controller interface circuit comprises a first transmitter connected to a first signal line and a second signal line; and a first receiver connected to the first signal line, and the first control signal and the second control signal are respectively transmitted to the non-volatile memory device through the first signal line and the second signal line.

Systems, apparatuses and methods include technology that identifies whether a product of first and second digital numbers is associated with a positive value or a negative value. During a first clock phase, the technology sets a first reference voltage to have a first value or a second value based on whether the product is associated with the positive value or the negative value. During the first clock phase, the technology controls switches to supply the first reference voltage to first plates of capacitors. Each of the capacitors includes a respective first plate of the first plates and a second plate. Further, during the first clock phase, the technology controls the switches based on the first digital number to electrically connect at least one of the second plates to the first reference voltage and electrically connect at least one of the second plates to a second reference voltage.

Embodiments of the disclosure, there is provided a method, a system for adjusting the memory, and a semiconductor device. The method for adjusting the memory includes: acquiring a mapping relationship between a temperature of a transistor, an equivalent width-length ratio of a sense amplifier transistor in a sense amplifier and an actual time at which the data is written into the memory; acquiring a current temperature of the transistor; and adjusting the equivalent width-length ratio, based on the current temperature and the mapping relationship, so that the actual time at which the data is written into the memory corresponding to the adjusted equivalent width-length ratio is within a preset writing time.

A memory circuit includes a pre-charging circuit and a control circuit. The pre-charging circuit includes a first pre-charging unit, a second pre-charging unit, a first power supply terminal, a second power supply terminal, a first control terminal, a second control terminal and a data terminal; the first pre-charging unit is connected with the first power supply terminal, the first control terminal and the data terminal; the second pre-charging unit is connected with the second power supply terminal, the second control terminal and the data terminal. The control circuit is configured to in response to a memory being in a row active state and not performing a reading-writing operation, control, through the second pre-charging unit, the data terminal and the second power supply terminal to be disconnected, and control, through the first pre-charging unit, the data terminal and the first power supply terminal to be disconnected.

A memory device according to the present invention comprises: a memory cell array in which memory cells are connected to wordlines and bitlines in a matrix form; and a control circuit for programming the memory cells or controlling a read operation, according to a start address, a burst length, a latency length, and a program or read command which are transmitted from a host, wherein the control circuit may comprise: a pulse generation unit for generating register pulses and counter pulses in synchronization with an operation clock; and a counter that sets the start address in synchronization with the register pulses, counts the number of counter pulses corresponding to the sum of the latency length and the burst length, and increases an address from the start address to the sum of the start address and the burst length.

A method of operating a memory device includes receiving a duty training request, performing first training for a write path in a first period, storing a result value of the first training, performing second training for a write path in a second period, storing a result value of the second training, transmitting the result value of the first training to an external device, and receiving a duty cycle adjuster (DCA) code value corresponding to the first training result value from the external device.

A memory device includes an external information input circuit configured to generate a burst mode signal and a write command pulse for a write operation, by receiving external information for the write operation; and a write operation control circuit configured to generate a write control pulse for storing internal data in a cell array, from the write command pulse when a first burst mode is performed on the basis of the burst mode signal, and to control whether to generate the write control pulse from the write command pulse when a second burst mode is performed on the basis of the burst mode signal.

A microelectronic device comprises a microelectronic device structure comprising a section comprising page buffers, and an additional section horizontally neighboring the section and comprising page buffer drivers and a timing delay chain coupled to the page buffer drivers. Each of the page buffer drivers is coupled to different group of the page buffers than each other of the page buffer drivers. The timing delay chain comprises timing delay circuits coupled in series with one another. Each of the timing delay circuits is configured to adjustably delay propagation of a control signal therethrough. Memory devices, methods of operating memory devices, and electronic systems are also described.

Apparatuses and methods of DLL measurement initialization are disclosed. An example apparatus includes: a clock enable circuit that provides a first clock signal having a half frequency of an input clock signal and second clock signals having a quarter frequency of the input clock signal; a coarse delay that provides the first clock signal with a coarse delay; a fine delay that provides the first clock signal with the coarse delay and a fine delay as an output clock signal; a model delay having a feedback delay equivalent to a sum of delays of an input stage and an output stage, and provides a feedback signal that is the output clock signal with the feedback delay; and a measurement initialization circuit that performs measurement initialization. The measurement initialization circuit includes synchronizers that receive the feedback signal and the second clock signals, and provide a stop signal to the coarse delay.