An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. The second channel includes a second command control circuit independent of the first command control circuit. The calibration circuit is shared by the first channel and the second channel to generate a calibration code responsive to a calibration command generated responsive to a first calibration command from the first command control circuit and a second calibration command from the second command control circuit.

A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NOR architecture in which vertical NOR strings are formed of multiple memory cells connected in parallel between a source line and a bit line. Weights of the neural network are encoded as threshold voltages of the memory cells and activations are encoded as word line voltages applied to the memory cells of the NOR strings. The memory cells are operated in the subthreshold region, where the word line voltages are below the threshold voltages. The NOR structure naturally sums the resultant subthreshold currents of the individual memory cells to generate the product of the activations and the weights of the neural network by concurrently applying input voltages to multiple memory cells of a NOR string.

A semiconductor memory device, and a method of operation, includes a memory block including a plurality of memory strings. The semiconductor memory device also includes a peripheral circuit performing a main program operation on drain select transistors included in the memory block, and a test program operation and a threshold voltage monitoring operation on memory cells included in the memory block. The semiconductor memory device further includes control logic controlling the peripheral circuit to detect a disturb susceptible memory string, among the plurality of memory strings, based on a result of performing the threshold voltage monitoring operation on the memory cells, and to perform an additional program operation on a drain select transistor included in the disturb susceptible memory string.

A content addressable memory (CAM) circuit includes a word line driver that incorporates a digital-to-analog converters (DAC), which enables the CAM circuit to store an n-bit value only with n CAM cells. The CAM circuit includes one or more of CAM cells configured to store bit values, at least one word line driver coupled to word lines of the CAM cells and configured to supply word line output to drive the CAM cells, and at least one bit line driver coupled to bit lines of the CAM cells and configured to supply bit line outputs to drive the CAM cells. The word line driver and the bit line driver include DAC circuits that includes PFETs and NFETs.

A storage device, including a volatile memory; a non-volatile memory; and a storage controller: wherein, based on detecting a power loss corresponding to the storage device, the storage controller is configured to: obtain a word stored in the volatile memory; write the word to a first word line; compare a number of unprogrammed cells to a first threshold number and a second threshold number, wherein the unprogrammed cells correspond to remainder data; based on determining that the number of unprogrammed cells is less than or equal to the first threshold number and greater than the second threshold number, determine whether to continue writing the word to the first word line by providing information about the first word line to a machine learning model; and based on determining not to continue writing the word to the first word line, write the remainder data to a second word line.