Systems, methods, circuits, and apparatuses for managing integrated circuits in memory devices are provided. In one aspect, an integrated circuit includes: a latch circuit including a latch and a sensing transistor coupled to the latch, and a compensation circuit coupled to the sensing transistor. The sensing transistor includes a gate terminal coupled to a sensing node and an additional terminal coupled to the compensation circuit, and the compensation circuit is configured to apply a control voltage to the additional terminal to compensate for a variation of a threshold voltage of the sensing transistor.

Disclosed is a memory device including a magnetic memory element. The memory device includes a memory cell array including a first region and a second region, the second region configured to store a value of a write voltage, the write voltage based on a value of a reference resistor for determining whether a programmed memory cell is in a parallel state or anti-parallel state, a voltage generator configured to generate a code value based on the value of the write voltage, and a write driver configured to drive a write current based on the code value, the write current being a current for storing data in the first region.

A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.

A semiconductor memory device includes a substrate, a ground selection line, a word line, an insulating layer, a vertical channel portion, and a first peripheral circuit gate pattern. The substrate includes a cell array region and a peripheral circuit region. The ground selection line is on the cell array region. The word line is on the ground selection line. The insulating layer is between the ground selection line and the word line. The vertical channel portion penetrates the ground selection line, word line, and insulating layer in a direction vertical to a top surface of the substrate. The first peripheral circuit gate pattern is on the peripheral circuit region of the substrate. The insulating layer extends from the cell array region onto the peripheral circuit region to cover a top surface of the first peripheral circuit gate pattern.

A method of controlling a memory device including a temperature sensor includes sensing a temperature of the memory device and extracting an extracted temperature for controlling the memory device using the sensed temperature, storing the extracted temperature in the memory device, calculating an estimated temperature at a current time point using the extracted temperature and a plurality of past extracted temperatures stored in the memory device, and controlling the memory device using the estimated temperature.

A semiconductor memory device includes a substrate, a ground selection line, a word line, an insulating layer, a vertical channel portion, and a first peripheral circuit gate pattern. The substrate includes a cell array region and a peripheral circuit region. The ground selection line is on the cell array region. The word line is on the ground selection line. The insulating layer is between the ground selection line and the word line. The vertical channel portion penetrates the ground selection line, word line, and insulating layer in a direction vertical to a top surface of the substrate. The first peripheral circuit gate pattern is on the peripheral circuit region of the substrate. The insulating layer extends from the cell array region onto the peripheral circuit region to cover a top surface of the first peripheral circuit gate pattern.

A magnetic configuration utilizing a plurality of posts and spiting the primary winding on each of the posts defining a core and placing the secondary windings together with the rectifier means around each post to minimise the stray and leakage inductance. A significant reduction of the core material and a reduction of the footprint is achieved due to better utilization of the winding material. The magnetic field is weaving from and through one post to the other to minimize the vertical component of ther field and forcing the magnetic field to be parallel with the winding to reduce the AC losses in copper of the winding. These properties allow the magnetic structure to be suitable in very high frequency applications and even in application with an air core. These magnetic structures can be used for implementing a transformer and for inductive applications.

A magnetic configuration utilizing a plurality of posts and spiting the primary winding on each of the posts defining a core and placing the secondary windings together with the rectifier means around each post to minimise the stray and leakage inductance. A significant reduction of the core material and a reduction of the footprint is achieved due to better utilization of the winding material. The magnetic field is weaving from and through one post to the other to minimize the vertical component of ther field and forcing the magnetic field to be parallel with the winding to reduce the AC losses in copper of the winding. These properties allow the magnetic structure to be suitable in very high frequency applications and even in application with an air core. These magnetic structures can be used for implementing a transformer and for inductive applications.

A random number generator capable of generating a natural random number using a spin-orbit torque (SOT) is provided. The random number generator includes a ferromagnetic metal layer and a spin-orbit torque wiring extending in a first direction crossing a lamination direction of the ferromagnetic metal layer and being joined to the ferromagnetic metal layer, wherein the direction of spins injected from the spin-orbit torque wiring into the ferromagnetic metal layer and an easy magnetization direction of the ferromagnetic metal layer intersect each other.

A volatile memory device includes a refresh controller configured to control a hidden refresh operation performed on a first portion of memory cells while a valid operation is performed on a second portion of the memory cells. The volatile memory device is configured to perform a regular refresh operation in response to receiving a refresh command. The refresh controller is configured to generate refresh information using a performance indicator of the hidden refresh operation during a first part of a reference time. The volatile memory device is configured to perform a desired number of the regular refresh operation during a remaining part of the reference time based on the refresh information. The desired number of the regular refresh operation is an integer based on a difference between a target number of refresh operations during the reference time and a count value of the hidden refresh operation during the reference time.