Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.

Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.

A spin orbit torque (SOT) memory device includes a SOT electrode having a spin orbit coupling material. The SOT electrode has a first sidewall and a second sidewall opposite to the first sidewall. The SOT memory device further includes a magnetic tunnel junction device on a portion of the SOT electrode. A first MTJ sidewall intersects the first SOT sidewall and a portion of the first MTJ sidewall and the SOT sidewall has a continuous first slope. The MTJ device has a second sidewall that does not extend beyond the second SOT sidewall and at least a portion of the second MTJ sidewall has a second slope.

A spin orbit torque (SOT) memory device includes a SOT electrode having a spin orbit coupling material. The SOT electrode has a first sidewall and a second sidewall opposite to the first sidewall. The SOT memory device further includes a magnetic tunnel junction device on a portion of the SOT electrode. A first MTJ sidewall intersects the first SOT sidewall and a portion of the first MTJ sidewall and the SOT sidewall has a continuous first slope. The MTJ device has a second sidewall that does not extend beyond the second SOT sidewall and at least a portion of the second MTJ sidewall has a second slope.

Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

Methods, systems, and devices for enabling fast pulse operation are described. A threshold voltage of a selection component and a requisite duration for a voltage applied to a selection component to reach a threshold voltage in response to a voltage generated by an external source may be determined. The threshold voltage may correspond to a voltage at which the selection component is configured to release electric charge. A voltage may then be generated and applied to an access line that is in electronic communication with the selection component and a memory cell for at least the requisite duration. Electric charge may be stored at the selection component during the requisite duration and transferred to memory cell after the requisite duration.

An electronic device includes a semiconductor memory. The semiconductor memory includes a memory cell array of a plurality of memory cells each including a variable resistance element and outputting, to a corresponding bit line, a cell voltage corresponding to a resistance value of the variable resistance element; a driving control circuit operable to control a reference data to be written in a selected memory cell among the memory cells, during a sensing operation; a resistance monitoring circuit operable to receive the cell voltage of the selected memory cell and output a monitoring voltage based on the cell voltage at the bit line, the monitoring voltage corresponding to a change in the resistance value during the sensing operation; and an amplifying circuit operable to amplify the monitoring voltage and output an amplified monitoring voltage as output data.