Various aspects relate to a memory cell including a field-effect transistor structure and a capacitive memory structure, wherein the capacitive memory structure includes at least one spontaneously polarizable memory element, and wherein the field-effect transistor structure includes a source region, a drain region, a channel region extending between the source region and the drain region, and a gate structure disposed at the channel region, wherein the gate structure of the field-effect transistor structure substantially overlaps the source region of the field-effect transistor structure and/or the drain region of the field-effect transistor structure.

Disclosed is a memory device which includes a plurality of memory banks and control logic. The control logic receives a plurality of column address bits and a plurality of read commands. The control logic includes a processing-in-memory (PIM) address generator. In a first operation mode, the control logic sends the plurality of column address bits to a memory bank. In a second operation mode, when the PIM address generator receives a first read command of the plurality of read commands, the control logic sends, to the memory bank, a first PIM address generated based on remaining column address bits other than some column address bits of the plurality of column address bits.

The invention provides a non-volatile storage element and non-volatile storage device employing a ferroelectric material with low power consumption, excellent high reliability, and especially write/erase endurance, which can be mixed with advanced CMOS logic. The non-volatile storage element has at least a first conductive layer, a second conductive layer, and a ferroelectric layer composed of a metal oxide between both conductive layers, with a buffer layer having oxygen ion conductivity situated between the ferroelectric layer and the first conductive layer and/or second conductive layer. An interface layer composed of a single-layer film or a multilayer film may be also provided between the first conductive layer and the ferroelectric layer, the interface layer as a whole having higher dielectric constant than silicon oxide, and when the buffer layer is present between the first conductive layer and the ferroelectric layer, the interface layer is situated between the first conductive layer and the buffer layer. The non-volatile storage device comprises at least a memory cell array comprising low-power-consumption ferroelectric memory elements formed in a two-dimensional or three-dimensional configuration, and a control circuit. The ferroelectric layer is scalable to 10 nm or smaller and is fabricated at a low temperature of ≤400° C., and is subjected to low temperature thermal annealing treatment at ≤400° C. after the buffer layer has been formed, to provide high reliability.

The invention provides a non-volatile storage element and non-volatile storage device employing a ferroelectric material with low power consumption, excellent high reliability, and especially write/erase endurance, which can be mixed with advanced CMOS logic. The non-volatile storage element has at least a first conductive layer, a second conductive layer, and a ferroelectric layer composed of a metal oxide between both conductive layers, with a buffer layer having oxygen ion conductivity situated between the ferroelectric layer and the first conductive layer and/or second conductive layer. An interface layer composed of a single-layer film or a multilayer film may be also provided between the first conductive layer and the ferroelectric layer, the interface layer as a whole having higher dielectric constant than silicon oxide, and when the buffer layer is present between the first conductive layer and the ferroelectric layer, the interface layer is situated between the first conductive layer and the buffer layer. The non-volatile storage device comprises at least a memory cell array comprising low-power-consumption ferroelectric memory elements formed in a two-dimensional or three-dimensional configuration, and a control circuit. The ferroelectric layer is scalable to 10 nm or smaller and is fabricated at a low temperature of ≤400° C., and is subjected to low temperature thermal annealing treatment at ≤400° C. after the buffer layer has been formed, to provide high reliability.

Methods, systems, and devices for ferroelectric memory plate power reduction are described. A plate line may be coupled with a voltage source, a capacitor, and one or more sections of a bank of ferroelectric memory cells. During a write operation, the capacitor may be discharged onto the plate line and the resulting voltage may be adjusted (e.g., increased) by the voltage source before writing one or more memory cells. During a write-back operation, a capacitor associated with one or more memory cells may be discharged onto the plate line and stored at the capacitor. The charge may be re-applied to the plate line and adjusted (e.g., increased) by the voltage source during the write-back.

The present invention relates to a neuromimetic network comprising a set of neurons and a set of synapses, at least one neuron comprising a first stack of superimposed layers, the first stack successively comprising: a first electrode, a first barrier layer made of an electrically insulating material, and a second electrode, the first electrode, the first barrier layer and the second electrode forming a first ferroelectric tunnel junction, at least one synapse comprising a second stack of superimposed layers, the second stack successively comprising: a third electrode, a second barrier layer made of an electrically insulating material, and a fourth electrode, the third electrode, the second barrier layer and the fourth electrode forming a second ferroelectric tunnel junction.

Dual-precision analog memory cells and arrays are provided. In some embodiments, a memory cell, comprises a non-volatile memory element having an input terminal and at least one output terminal; and a volatile memory element having a plurality of input terminals and an output terminal, wherein the output terminal of the volatile memory element is coupled to the input terminal of the non-volatile memory element, and wherein the volatile memory element comprises: a first transistor coupled between a first supply and a common node, and a second transistor coupled between a second supply and the common node; wherein the common node is coupled to the output terminal of the volatile memory element; and wherein gates of the first and second transistors are coupled to respective ones of the plurality of input terminals of the volatile memory element.

Memory devices and methods of operating memory devices in which maintenance operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., operations in excess of a predetermined threshold) warrants a maintenance operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of operations at the memory location, to schedule a maintenance operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled maintenance operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further operations at the memory location until after the count has been decreased.

Various aspects relate to a method of manufacturing a memory cell, the method including: forming a memory cell, wherein the memory cell comprises a spontaneously-polarizable memory element, wherein the spontaneously-polarizable memory element is in an as formed condition; and carrying out a preconditioning operation of the spontaneously-polarizable memory element to bring the spontaneously-polarizable memory element from the as formed condition into an operable condition to allow for a writing of the memory cell after the preconditioning operation is carried out.

Methods, systems, and devices for configurable input for an amplifier are described. In some examples, a circuit may be configured to operate based on a signal having a first voltage profile or a second voltage profile. For example, the first voltage profile may be associated with a range of voltages that are based on a temperature of an associated memory chip, and the second voltage profile may be associated with a voltage (or voltages) that are not associated with the temperature of the memory chip. The circuit may include one or more transistors and switches that are activated based on the voltage profile and a switch receiving a particular control signal. In some instances, the control signal may be received based on a value stored to one or more non-volatile memory elements.