A memory device with a novel structure that is suitable for a register file is provided. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit includes a first logic element and a second logic element each of which is configured to perform logic inversion, a selection circuit, a first switch, a second switch, and a third switch. The second memory circuit includes a first transistor in which a channel formation region is provided in an oxide semiconductor film, a second transistor, and a capacitor to which a potential is supplied through the first transistor.

In a configuration including a memory cell that retains multilevel data by controlling the on/off state of a transistor, correct data can be read out even if a potential of data retained by turning off the transistor is changed. The memory cell controls writing or retention of data corresponding to one of a plurality of potentials by controlling an on/off state of the transistor. The write voltage generator circuit outputs a first write voltage of data to be written to the memory cell. The write voltage generator circuit obtains a read voltage of the data by reading the first write voltage written to the memory cell. The write voltage generator circuit generates a second write voltage by correcting a change of the first write voltage caused by turning off the transistor, and outputs the second write voltage to the memory cell.

In a configuration including a memory cell that retains multilevel data by controlling the on/off state of a transistor, correct data can be read out even if a potential of data retained by turning off the transistor is changed. The memory cell controls writing or retention of data corresponding to one of a plurality of potentials by controlling an on/off state of the transistor. The write voltage generator circuit outputs a first write voltage of data to be written to the memory cell. The write voltage generator circuit obtains a read voltage of the data by reading the first write voltage written to the memory cell. The write voltage generator circuit generates a second write voltage by correcting a change of the first write voltage caused by turning off the transistor, and outputs the second write voltage to the memory cell.

A novel semiconductor device, a semiconductor device capable of storing multi-level data, a semiconductor device with low power consumption, a semiconductor device with a reduced area, or a highly reliable semiconductor device is provided. The semiconductor device includes a memory cell which includes a first transistor and a capacitor, and a second transistor. The first transistor includes an oxide semiconductor in a channel formation region. One of a source and a drain of the first transistor is electrically connected to a first wiring. The other of the source and the drain of the first transistor is electrically connected to one of electrodes of the capacitor. The other of the electrodes of the capacitor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to the first wiring.

A novel semiconductor device, a semiconductor device capable of storing multi-level data, a semiconductor device with low power consumption, a semiconductor device with a reduced area, or a highly reliable semiconductor device is provided. The semiconductor device includes a memory cell which includes a first transistor and a capacitor, and a second transistor. The first transistor includes an oxide semiconductor in a channel formation region. One of a source and a drain of the first transistor is electrically connected to a first wiring. The other of the source and the drain of the first transistor is electrically connected to one of electrodes of the capacitor. The other of the electrodes of the capacitor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to the first wiring.

The present disclosure relates to reference and sense architecture in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes word line (WL) switch circuitry configured to select a global WL (GWL) and a local WL (LWL) associated with the target memory cell; bit line (BL) switch circuitry configured to select a global BL (GBL) and a local BL (LBL) associated with the target memory cell; and sense circuitry including a first sense circuitry capacitance and a second sense circuitry capacitance, the sense circuitry configured to precharge the selected GWL, the LWL and the first sense circuitry capacitance to a WL bias voltage WLVDM, produce a reference voltage (V.sub.REF) utilizing charge on the selected GWL and charge on the first sense circuitry capacitance and determine a state of the target memory cell based, at least in part, on V.sub.REF and a detected memory cell voltage V.sub.LWL.

A semiconductor memory device includes a memory array including a plurality of element blocks, the plurality of element blocks including end-portion element blocks arranged at an end portion of the memory array, and at least one dummy block disposed adjacent to the end-portion element blocks, the at least one dummy block being not in practical use. A layout pattern of the at least one dummy block is configured to correspond to only a portion of a layout pattern of the plurality of element blocks.

Provided is a semiconductor device including first to sixth capacitors, first to fourth wirings, first and second sense amplifiers, and a memory cell array over the first and second sense amplifiers. The first wiring is electrically connected to the memory cell array, one electrode of the first capacitor, the third wiring via a source and a drain of a first transistor, the fourth wiring via the fifth capacitor, and the second wiring via the first sense amplifier. The second wiring is electrically connected to one electrode of the second capacitor, the fourth wiring via a source and a drain of a second transistor, and the third wiring via the sixth capacitor. The third wiring is electrically connected to one electrode of the third capacitor, and the fourth wiring via the second sense amplifier. The fourth wiring is electrically connected to one electrode of the fourth capacitor.

Provided is a semiconductor device including first to sixth capacitors, first to fourth wirings, first and second sense amplifiers, and a memory cell array over the first and second sense amplifiers. The first wiring is electrically connected to the memory cell array, one electrode of the first capacitor, the third wiring via a source and a drain of a first transistor, the fourth wiring via the fifth capacitor, and the second wiring via the first sense amplifier. The second wiring is electrically connected to one electrode of the second capacitor, the fourth wiring via a source and a drain of a second transistor, and the third wiring via the sixth capacitor. The third wiring is electrically connected to one electrode of the third capacitor, and the fourth wiring via the second sense amplifier. The fourth wiring is electrically connected to one electrode of the fourth capacitor.

An unified IC system includes a base memory chip, a plurality of stacked memory chips, and a logic chip. The base memory chip includes a memory region and a bridge area, the memory region includes a plurality of memory cells, and the bridge area includes a plurality of memory input/output (I/O) pads and a plurality of third transistors. The plurality of stacked memory chips is positioned above the base memory chip. The logic chip includes a logic bridge area and a plurality of second transistors, the logic bridge includes a plurality of logic I/O pads, wherein the plurality of memory I/O pads are electrically coupled to the plurality of logic I/O pads, and a voltage level of an I/O signal of the third transistor is the same or substantially the same as a voltage level of an I/O signal of the second transistor.