Novel and useful quantum structures having a continuous well with control gates that control a local depletion region to form quantum dots. Local depleted well tunneling is used to control quantum operations to implement quantum computing circuits. Qubits are realized by modulating gate potential to control tunneling through local depleted region between two or more sections of the well. Complex structures with a higher number of qdots per continuous well and a larger number of wells are fabricated. Both planar and 3D FinFET semiconductor processes are used to build well to gate and well to well tunneling quantum structures. Combining a number of elementary quantum structure, a quantum computing machine is realized. An interface device provides an interface between classic circuitry and quantum circuitry by permitting tunneling of a single quantum particle from the classic side to the quantum side of the device. Detection interface devices detect the presence or absence of a particle destructively or nondestructively.

Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 μA/μm.sup.2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.

Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 μA/μm.sup.2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.

The invention describes a memory device which combines a switchable resistive element and a superconductor element electrically in parallel. The switchable resistive element comprises an active material, which is switchable between first and second values of electrical resistivity ρ.sub.1 and ρ.sub.2 at the same temperature, wherein ρ.sub.1 is different to ρ.sub.2. The superconductor element is operable so that at least part of the superconductor element is switchable from a superconducting state to a non-superconducting state. When the superconductor element is switched from the superconducting state to the non-superconducting state, a current injection is provided through the switchable resistive element capable of switching the switchable resistive element between said first and second values of electrical resistivity.

The invention describes a memory device which combines a switchable resistive element and a superconductor element electrically in parallel. The switchable resistive element comprises an active material, which is switchable between first and second values of electrical resistivity ρ.sub.1 and ρ.sub.2 at the same temperature, wherein ρ.sub.1 is different to ρ.sub.2. The superconductor element is operable so that at least part of the superconductor element is switchable from a superconducting state to a non-superconducting state. When the superconductor element is switched from the superconducting state to the non-superconducting state, a current injection is provided through the switchable resistive element capable of switching the switchable resistive element between said first and second values of electrical resistivity.

A superconducting memory circuit for applying and propagating superconducting signals through a plurality of superconducting wires in the memory circuit is provided. The memory circuit includes multiple passive cells arranged in a plurality of sets. Each set of passive cells has associated therewith at least one common superconducting wire interconnecting a subset of the passive cells in the set of passive cells. The memory circuit further including at least one power-signal propagation circuit, an input of the power-signal propagation circuit being coupled with a preceding set of passive cells via a first superconducting wire, and an output of the power-signal propagation circuit being coupled with a subsequent set of passive cells via a second superconducting wire. Upon application of a first superconducting signal to the first superconducting wire, the power-signal propagation circuit applies a second superconducting signal to the second superconducting wire.

A superconducting memory circuit for applying and propagating superconducting signals through a plurality of superconducting wires in the memory circuit is provided. The memory circuit includes multiple passive cells arranged in a plurality of sets. Each set of passive cells has associated therewith at least one common superconducting wire interconnecting a subset of the passive cells in the set of passive cells. The memory circuit further including at least one power-signal propagation circuit, an input of the power-signal propagation circuit being coupled with a preceding set of passive cells via a first superconducting wire, and an output of the power-signal propagation circuit being coupled with a subsequent set of passive cells via a second superconducting wire. Upon application of a first superconducting signal to the first superconducting wire, the power-signal propagation circuit applies a second superconducting signal to the second superconducting wire.

A memory cell having a Josephson junction and a magnetic junction situated in a close proximity to the Josephson junction. The two junctions may be vertically integrated. The magnetic junction has at least two magnetic layers with different coercive forces and a non-magnetic layer therebetween, to form a spin valve or pseudo-spin valve. A magnetization direction of a magnetic layer with lower coercive force can be rotated with respect to the larger coercive force magnetic layer(s). Magnetic fields produced by appropriately configured control lines carrying electric current, or spin-polarized current through the magnetic junction, can result in rotation. The magnetic junction influences the Josephson critical current of the Josephson junction, leading to distinct values of critical current which can serve as digital logic states. The so obtained memory cell can be integrated into the large arrays containing a plurality of the cells, to enable the selective READ and WRITE operations.

A memory cell having a Josephson junction and a magnetic junction situated in a close proximity to the Josephson junction. The two junctions may be vertically integrated. The magnetic junction has at least two magnetic layers with different coercive forces and a non-magnetic layer therebetween, to form a spin valve or pseudo-spin valve. A magnetization direction of a magnetic layer with lower coercive force can be rotated with respect to the larger coercive force magnetic layer(s). Magnetic fields produced by appropriately configured control lines carrying electric current, or spin-polarized current through the magnetic junction, can result in rotation. The magnetic junction influences the Josephson critical current of the Josephson junction, leading to distinct values of critical current which can serve as digital logic states. The so obtained memory cell can be integrated into the large arrays containing a plurality of the cells, to enable the selective READ and WRITE operations.

A superconducting memory cell includes a magnetic Josephson junction (MJJ) with a ferromagnetic material, having at least two switchable states of magnetization. The binary state of the MJJ manifests itself as a pulse appearing, or not appearing, on the output. A superconducting memory includes an array of memory cells. Each memory cell includes a comparator with at least one MJJ. Selected X and Y-directional write lines in their combination are capable of switching the magnetization of the MJJ. A superconducting device includes a first and a second junction in a stacked configuration. The first junction has an insulating layer barrier, and the second junction has an insulating layer sandwiched in-between two ferromagnetic layers as barrier. An electrical signal inputted across the first junction is amplified across the second junction.