Magnetic random access memory (MRAM) cells are provided. An MRAM cell includes a plurality of stacked magnetic tunnel junction (MTJ) devices coupled in serial and a transistor. The transistor having a gate coupled to a word line, a first terminal coupled to a bit line through the stacked MTJ devices, and a second terminal coupled to a source line. The stacked MTJ devices are different sizes.

An information processing device includes: a memory; and a processor configured to: hold each of values of state variables included in an evaluation function representing energy; calculate the change value of the energy for each of state transitions, when a state transition occurs due to a change of any of the values of the state variables; control a temperature value representing temperature; select any of the state transitions, based on priority information set based on state transition information updated last time with respect to identification information for identifying each state transition, and transition acceptance information indicating transition acceptance determined based on the change value, and a generated thermal noise; and output a lowest energy state which is the values of the state variables when the energy to be updated based on the selected state transition becomes a lowest value.

According to an aspect there is provided a memory cell. The memory cell comprises: a first and a second electrode; a spin-orbit-torque, SOT, layer comprising a first and a second electrode contact portion arranged in contact with the first and the second electrode, respectively, and an intermediate portion between the first and second electrode contact portions; a first magnetic tunnel junction, MTJ, layer stack arranged in contact with the intermediate portion; and a second MTJ layer stack arranged in contact with the second electrode contact portion and directly above the second electrode.

A memory device comprising such a memory cell and a method for writing to such a memory cell are also provided.

A circuit may include a memory cell. The memory cell may include a first memory element, a second memory element, a first transistor, and a second transistor. The first memory element may be connected to a bit line. The second memory element may be connected to a select line. The first transistor may be connected to a first word line. The second transistor may be connected to a second word line. The first memory element may be programmed by applying a first write voltage to the bit line, applying a second write voltage to the second word line, applying a first intermediate voltage to the select line, and applying a second intermediate voltage to the first word line. The select line may be connected to a high impedance. The first write voltage may be a positive supply voltage, the second write voltage may be a negative supply voltage.

A spin-orbit torque device 100 is described. In an embodiment, the spin-orbit torque device 100 comprises: a first pinning region 106 having a first fixed magnetization direction; a second pinning region 108 having a second fixed magnetization direction which is in a different direction to the first fixed magnetization direction; a magnetic layer 102 having a switchable magnetization direction; and a spin source layer 104 configured to generate a spin current for propagating a domain wall between the first and second pinning regions 106, 108 to switch the switchable magnetization direction of the magnetic layer 102 between the first and second fixed magnetization directions.

A spin-orbit torque (SOT)-MRAM comprising a first magnetic tunneling junction (MTJ) having a first diameter and having a first critical voltage. A second MTJ having a second diameter and having a second critical voltage, wherein the first diameter and the second diameter are different, wherein the first critical voltage and the second critical voltages are different. A metal rail in direct contact with the first MTJ and the second MTJ, wherein the metal rail injects a spin current in to both the first MTJ and the second MTJ.

Structures including non-volatile memory elements and methods of fabricating a structure including non-volatile memory elements. First, second, and third non-volatile memory elements each include a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. A first bit line is coupled to the first electrode of the first non-volatile memory element and to the first electrode of the second non-volatile memory element. A second bit line is coupled to the first electrode of the third non-volatile memory element.

A circuit includes an array of OTP cells, an array of NVM cells, an amplifier coupled to each of the array of OTP cells and the array of NVM cells, and a control circuit configured to generate one or more control signals. Responsive to the one or more control signals, the amplifier is configured to generate an output voltage based on a current received from the array of OTP cells in a first configuration, and generate the output voltage based on a voltage received from the array of NVM cells in a second configuration.

An image sensor includes a semiconductor substrate including a first surface and a second surface and further includes a well region and a first floating diffusion region that are each adjacent to the first surface. The image sensor includes a first vertical transmission gate and a second vertical transmission gate isolated from direct contact with each other and each extend from the first surface of the semiconductor substrate and in a thickness direction of the semiconductor substrate through at least a portion of the well region. The image sensor includes a first storage gate between the first vertical transmission gate and the first floating diffusion region and on the first surface of the semiconductor substrate. The image sensor includes a first tap transmission gate between the first storage gate and the first floating diffusion region and on the first surface of the semiconductor substrate.

A semiconductor storage device including a first magnetoresistive memory and a second magnetoresistive memory that are two types of magnetoresistive memories accessed by a target logic unit that is one logic unit. The target logic unit Ω the first magnetoresistive memory, and the second magnetoresistive memory are formed on one semiconductor chip, and the first magnetoresistive memory has a larger coercive force than the second magnetoresistive memory.