Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.

The present disclosure is drawn to, among other things, an antifuse circuit. The antifuse circuit includes a plurality of antifuse bitcells and a reference resistor. Each antifuse bitcell includes two or more memory bits and a reference resistor. The two or more memory bits are configured to be in a programmed state and at least one unprogrammed state.

Provided is a magnetoresistive random-access memory (MRAM) cell. The MRAM cell comprises a first heavy metal layer and a first magnetic tunnel junctions (MTJ) coupled to the first heavy metal layer. The first MTJ has a first area. The MRAM cell further comprises a second MTJ. The second MTJ is connected in series with the first MTJ, and the second MTJ has a second area that is different than the first area. The second MTJ shared a reference layer with the first MTJ. The MRAM cell further comprises a second heavy metal layer that is coupled to the second MTJ.

Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a BNN is stored in a pair of series connected memory cells. A binary input is applied as a pattern of voltage values on a pair of word lines connected to the unit synapse to perform the multiplication of the input with the weight by determining whether or not the unit synapse conducts. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a counter.

In some examples, a device includes a dielectric material, a ferromagnetic material, and a topological material positioned between the dielectric material and the ferromagnetic material. The device is configured to trap electric charge inside the dielectric material or at an interface of the dielectric material and the topological material. The device is configured to switch a magnetization state of the ferromagnetic material based on a current through the topological material or based on a voltage in the topological material.

Provided is a method of operating a magnetic memory system. The method of operating the magnetic memory system includes: preparing a plurality of magnetic memory cells; classifying the magnetic memory cells into a plurality of magnetic memory cell groups by using program current values of the magnetic memory cells; constructing a magnetic memory system by hierarchizing the magnetic memory cell groups; and primarily performing programming by selecting one magnetic memory cell group from the hierarchized magnetic memory cell groups according to an external temperature.

A memory device includes a plurality of circuit layers, a plurality of first conductive through via structures and a plurality of bitlines. The circuit layers are disposed one above another, and each circuit layer includes one or more memory cell arrays. The first conductive through via structures penetrates though the circuit layers. Each of the bitlines includes a plurality of bitline segments disposed on the circuit layers respectively. The bitline segments are electrically connected through one of the first conductive through via structures. Each bitline segment is coupled to a plurality of memory cells of a memory cell array of a circuit layer where the bitline segment is disposed.

Magnetic random access memory (MRAM) cells are provided. An MRAM cell includes a plurality of stacked magnetic tunnel junction (MTJ) devices coupled in serial and a transistor. The transistor having a gate coupled to a word line, a first terminal coupled to a bit line through the stacked MTJ devices, and a second terminal coupled to a source line. The stacked MTJ devices are different sizes.

A magnetic domain device is provided in which a magnetic free layer (i.e., the storage layer) of a magnetic tunnel junction (MTJ) pillar is in close proximity to a conductive write line that is disposed beneath the MTJ pillar. The magnetic domain device further includes a pair of spaced apart bottom electrodes located beneath the conductive write line, and a top electrode located on the MTJ pillar. The magnetic domain device can be used in analog memories including multi-bit storage, analog memory for artificial intelligence (AI) applications.

A memory device, comprising a first magnetic anisotropy magnetic tunnel junction (ma-MTJ) having a first free layer disposed at one end thereof and a second ma-MTJ having a second free layer disposed at one end thereof. The first and second ma-MTJs are stacked with each other with the first free layer facing the second free layer. A tunneling barrier is sandwiched between the first and second free layer. A magnetic anisotropy direction of the first ma-MTJ is perpendicular to a magnetic anisotropy direction of the second ma-MTJ, and a magnetisation direction of the first free layer is perpendicular to a magnetisation direction of the second free layer.