Exemplary embodiments of the present disclosure provide a spin valve and a spintronic device comprising the same. The spin valve may comprise two or more magnetic layers stacked in sequence, wherein the spin valve further comprises at least one pair of nonmagnetic semiconductor layers arranged between any two adjacent magnetic layers among the two or more magnetic layers, wherein a built-in electric field is formed between the at least one pair of nonmagnetic semiconductor layers.

A memory system for performing a recovery operation is provided. A memory system includes a memory device including a plurality of memory cells constituting a plurality of sub-sets, and a memory controller for controlling the memory device. The memory controller controls the memory device to manage a read count indicating a number of read operations performed by the memory device for each of the plurality of sub-sets, and to perform a recovery operation on a sub-set, among the plurality of sub-sets, based on the read count corresponding to the read count. Each of a plurality of sub-sets includes a plurality of pages. Each of the plurality of pages is a unit in which a read operation is performed in the plurality of memory cells.

Disclosed is a memory device including a multi-bit perpendicular magnetic tunnel junction, wherein the multi-bit perpendicular magnetic tunnel junction includes an upper synthetic antiferromagnetic layer, pinned layer, lower dual free layer, and upper free layer formed in a laminated manner between a top electrode and a bottom electrode.

A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction.

A magnetic memory structure includes a heavy-metal layer, a plurality of magnetic tunneling junction (MTJ) layer, a conductive layer and an insulation layer. In an example, the pinned-layer of the MTJ layers are arranged in a string form and disposed over the barrier-layer. In an example also disclosed, the pinned-layer, the free-layer of the MTJ layers are arranged in a string form. Whereas the pinned-layers are disposed over the barrier-layer and the free-layers are disposed over the heavy-metal layer. The conductive layer is formed under the heavy-metal layer and includes a first conductive portion and a second conductive portion separated from each other and connected with two end of the heavy-metal layer respectively. The insulation layer fills up an interval between the first conductive portion and the second conductive portion. The conductive layer has an electric conductivity higher than that of the heavy-metal layer.

A magnetic tunnel junction includes at least one free layer, at least one reference layer, and at least one tunnel barrier separating the free layer and the reference layer, wherein the free layer is an inhomogeneous granular layer including at least two grains, each grain of the at least two grains being sensibly magnetically decoupled from the other adjacent grains of the at least two grains.

A circuit includes an OTP cell, an NVM cell, and a bit line coupled to the OTP cell, the NVM cell, and a first input terminal of an amplifier. The amplifier is configured to generate an output voltage based on a signal on the bit line, an ADC is configured to generate a digital output signal based on the output voltage, and a comparator includes a first input port coupled to an output port of the ADC and is configured to output a data bit responsive to a comparison of the digital output signal to a threshold level received at a second input port.

Methods, systems, and devices for programming techniques for polarity-based memory cells are described. A memory device may use a first type of write operation to program one or more memory cells to a first state and a second type of write operation to program one or more memory cells to a second state. Additionally or alternatively, a memory device may first attempt to use the first type of write operation to program one or more memory cells, and then may use the second type of write operation if the first attempt is unsuccessful.

A magnetic memory device includes a first electrode, a second electrode, and a layer stack located between the first electrode and the second electrode. The layer stack includes a reference layer, a tunnel barrier layer, a free layer, and a magnetoelectric multiferroic layer including at least one crystalline grain. The magnetization of the magnetoelectric multiferroic layer may be axial, canted, or in-plane. For axial or canted magnetization of the magnetoelectric multiferroic layer, a deterministic switching of the free layer may be achieved through coupling with the axial component of magnetization of the magnetoelectric multiferroic layer. Alternatively, the in-plane magnetization of the magnetoelectric multiferroic layer may be employed to induce precession of the magnetization angle of the free layer.

A metamagnetic tunneling-based spin valve device for multistate magnetic memory comprising an electronic memory logic element with four stable resistance states. A metamagnetic tunneling-based spin valve device for multistate magnetic memory comprising a layer of a metamagnetic material, a layer of a nonmagnetic material on the layer of a metamagnetic material, and a layer of a ferromagnetic material on the layer of a nonmagnetic material. A method of making a metamagnetic tunneling-based spin valve device for multistate magnetic memory.