The application discloses an integrated memory device, a manufacturing method and an operation method thereof. The integrated memory cell includes: a first memory cell; and an embedded second memory cell, serially coupled to the first memory cell, wherein the embedded second memory cell is formed on any one of a first side and a second side of the first memory cell.

Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.

A synapse of a neuromorphic device is provided. The synapse of the neuromorphic device may include a variable resistive device, a first transistor, and a second transistor. A drain electrode of the first transistor and a gate electrode of the second transistor may be electrically connected in common with a first electrode of the variable resistive device.

A floating memristor with a nano-battery between a top and bottom floating gates is disclosed. The floating memristor includes a nano-battery, a top floating gate assembly disposed on an anode of the nano-battery, and a bottom floating gate assembly disposed on a cathode of the nano-battery. The floating memristor is an artificial synapse. The top floating gate assembly and the anode of the nano-battery convert electric signal to ionic signal by tunneling effect and field effect to simulate a presynaptic membrane. The electrolyte of the nano-battery is an ionic channel as a synaptic gap. The anode and the bottom floating gate transfer the ionic signal to electric signal by field effect and tunneling effect to simulate a postsynaptic membrane.

The present disclosure includes apparatuses, methods, and systems for multi-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of a plurality of possible data states by applying a voltage pulse to the memory cell, determining the memory cell snaps back in response to the applied voltage pulse, turning off a current to the memory cell upon determining the memory cell snaps back, and applying a number of additional voltage pulses to the memory cell after turning off the current to the memory cell.

A floating memristor with a nano-battery between a top and bottom floating gates is disclosed. The floating memristor includes a nano-battery, a top floating gate assembly disposed on an anode of the nano-battery, and a bottom floating gate assembly disposed on a cathode of the nano-battery. The floating memristor is an artificial synapse. The top floating gate assembly and the anode of the nano-battery convert electric signal to ionic signal by tunneling effect and field effect to simulate a presynaptic membrane. The electrolyte of the nano-battery is an ionic channel as a synaptic gap. The anode and the bottom floating gate transfer the ionic signal to electric signal by field effect and tunneling effect to simulate a postsynaptic membrane.

According to one embodiment, a variable resistance element includes first and conductive layers and first and second layers. The first conductive layer includes a first element including at least one selected from the group consisting of silver, copper, aluminum, nickel, and titanium. The second conductive layer includes at least one selected from the group consisting of platinum, gold, iridium, tungsten, palladium, rhodium, titanium nitride, and silicon. A first layer contacts the first conductive layer, and is provided between the first and second conductive layers. The first layer includes a first material. The first material is insulative. The second layer includes a second element and a second material and is provided between the first layer and the second conductive layer. The second element includes at least one selected from the group consisting of silver, copper, aluminum, nickel, and titanium. The second material is different from the first material.

In one embodiment, a cached memory device can include: (i) a memory array coupled to a system address bus and an internal data bus; (ii) a plurality of data buffers coupled to a system data bus, and to the memory array via the internal data bus; (iii) a plurality of valid bits, where each valid bit corresponds to one of the data buffers; (iv) a plurality of buffer address registers coupled to the system address bus, where each buffer address register corresponds to one of the data buffers; and (v) a plurality of compare circuits coupled to the system address bus, where each compare circuit corresponds to one of the data buffers.

Memory circuitry comprises memory cells having two terminals and a feedback path connected between the two terminals. The feedback path is used to adaptively amplify identical programming pulses that serve to change memory states of the memory cell, and the amplification is based on a current resistive level of the memory cell, which may for example be a multi-level memory cell.

Technologies are generally described herein for a non-volatile static random access memory device with multiple storage states. In some examples, the multi-storage state non-volatile random access memory device has two or more memory cells. Each memory cell may include a pair of programmable resistive devices that may be dynamically programmed to configure the memory cell in a particular logic state.