A memory device having a first array of first electrodes extending along a first direction made from a first material and a second array of second electrodes extending along a second direction made from a second material. An intersection defined by the first array and the second array, wherein each intersection of the first array and the second array defines a two-terminal resistive memory cell, said memory cell formed by a conductive path between said first and second electrodes.

According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.

Technologies are generally described herein for a non-volatile static random access memory device with multiple storage states. In some examples, the multi-storage state non-volatile random access memory device has two or more memory cells. Each memory cell may include a pair of programmable resistive devices that may be dynamically programmed to configure the memory cell in a particular logic state.

A first memory cell including a phase change material. The first memory cell is programmable to store one data value of a plurality of data values. The plurality of data values are represented by a plurality of non-overlapping ranges of resistance of the first memory cell. At least one testing pulse is applied to the first memory cell to establish a cell resistance of the first memory cell in an intermediate range of resistance, the intermediate range of resistance in between first and second adjacent ranges in the plurality of non-overlapping ranges of resistance representing the plurality of data values. After applying the at least one testing pulse to the first memory cell, it is determined whether to apply at least one healing pulse to repair the first memory cell, depending on relative values of (i) the cell resistance in the intermediate range of resistance and (ii) a reference resistance in the intermediate range of resistance.

Two-terminal memory can be set to a first state (e.g., conductive state) in response to a program pulse, or set a second state (e.g., resistive state) in response to an erase pulse. These pulses generally produce a voltage difference between the two terminals of the memory cell. Certain electrical characteristics associated with the pulses can be manipulated in order to enhance the efficacy of the pulse. For example, the pulse can be enhanced or improved to reduce power-consumption associated with the pulse, reduce a number of pulses used to successfully set the state of the memory cell, or to improve Ion distribution associated with active metal particles included in the memory cell.

According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.

Providing for a high performance and efficiency NAND architecture is described herein. By way of example, a NAND array is disclosed comprising memory cells having a 1 transistor-1 two-terminal memory device (IT-1D) arrangement. Memory cells of the NAND array can be arranged electrically in serial with respect to each other, from source to drain. Moreover, respective memory cells comprise a transistor component connected in parallel to a two-terminal memory device. In some embodiments, a resistance of the activated transistor component is selected to be substantially less than that of the two-terminal memory device, and the resistance of the deactivated transistor component is selected to be substantially higher than the two-terminal memory device. Accordingly, by activating or deactivating the transistor component, a signal applied to the memory cell can be shorted past the two-terminal memory device, or directed through the two-terminal memory device, respectively.

A memory devices and methods can use multiple sense operations to detect a state of memory elements in a marginal state. In some embodiments, an evaluation circuit can generates an output value for a memory element in response multiple sense results for the same memory element.

In operating a resistive memory device including a number of memory cells, a write pulse is applied to each of the plurality of memory cells such that each of the memory cells has a target resistance state between a first reference resistance and a second reference resistance higher than the first reference resistance. The resistance of each of the memory cells is read by applying a verify pulse to each of the plurality of memory cells. A verify write current pulse is applied to each of the memory cells that has resistance higher than the second reference resistance, and a verify write voltage pulse is applied to each of the memory cells that has resistance lower than the first reference resistance.

A method of resetting a variable resistance memory cell in a nonvolatile memory device includes; programming the memory cell to a set state using a corresponding compliance current, and then programming the memory cell to a reset state by pre-reading the variable resistance memory cell to determine its resistance and resetting the memory cell using a variable reset voltage determined in response to the determined resistance.