A memory cell arrangement is provided that may include: one or more memory cells, each memory cell of the one or more memory cells including: a field-effect transistor structure; a plurality of first control nodes; a plurality of first capacitor structures, a second control node; and a second capacitor structure including a first electrode connected to the second control node and a second electrode connected to a gate region of the field-effect transistor. Each of the plurality of first capacitor structures includes a first electrode connected to a corresponding first control node of the plurality of first control nodes, a second electrode connected to the gate region of the field-effect transistor structure, and a spontaneous-polarizable region disposed between the first electrode and the second electrode of the first capacitor structure.

The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

A method of generating a multi-level signal having one of three or more voltage levels that are different from each other, the method including: performing a first voltage setting operation in which first and second voltage intervals are adjusted to be different from each other, wherein the first voltage interval represents a difference between a first pair of adjacent voltage levels and the second voltage interval represents a difference between a second pair of adjacent voltage levels; performing a second voltage setting operation in which a voltage swing width is adjusted, the voltage swing width representing a difference between a lowest and a highest voltage level among the three or more voltage levels; and generating an output data signal that is the multi-level signal based on input data including two or more bits, a result of the first voltage setting operation and a result of the second voltage setting operation.

Methods and devices for dynamic allocation of a capacitive component in a memory device are described. A memory device may include one or more voltage rails for distributing supply voltages to a memory die. A memory device may include a capacitive component that may be dynamically coupled to a voltage rail based on an identification of an operating condition on the memory die, such as a voltage droop on the voltage rail. The capacitive component may be dynamically coupled with the voltage rail to maintain the supply voltage on the voltage rail during periods of high demand. The capacitive component may be dynamically switched between voltage rails during operation of the memory device based on operating conditions associated with the voltage rails.

Methods, systems, and devices for system and method for reading and writing memory management data through a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.

A semiconductor memory device includes a memory cell array, an error correction circuit and a control logic circuit. The error correction circuit includes an error correction code (ECC) decoder to perform an ECC decoding on a codeword including a main data and a parity data, read from a target page of the memory cell array to correct errors in the read codeword. The control logic circuit controls the error correction circuit based on a command and address from an external memory controller. The ECC decoder has t-bit error correction capability, generates a syndrome based on the codeword using a parity check matrix, performs t iterations during (t−2) cycles to generate an error locator polynomial based on the syndrome, searches error positions in the codeword based on the error locator polynomial and corrects the errors in the codeword based on the searched error positions.

Apparatuses, systems, and methods for high-pass filtering pre-emphasis circuits. A device may use a pre-emphasis driver to provide a multi-level signal based on multiple binary signals. The pre-emphasis driver includes a primary driver coupled in parallel with at least one equalizer path, each of which includes an equalizer driver and a filtering element. The filtering element may be an AC filtering element, such as a capacitor. The equalizer paths may contribute equalized signal(s) which have a high-pass filtering behavior. The pre-emphasis circuit may combine the primary signal from the primary driver and the equalized signals to generate an overall output multi-level signal. In some embodiments, the pre-emphasis driver may be a pulse amplitude modulated (PAM) driver, such as a PAM4 driver with four levels of the multi-level driver.

A novel semiconductor device is provided. Alternatively a memory device which can retain more multi-level data is provided. One of a source or a drain of a write transistor is electrically connected to a bit line, and the other of the source or the drain of the write transistor is electrically connected to a data retaining portion. Data written to the data retaining portion is provided to the data retaining portion through a write bit line and the write transistor. Rising of a threshold voltage which is caused in a write operation can be inhibited and more multi-level data can be retained(stored) through electrically connecting a back gate of the write transistor to the write bit line.

Methods, systems, and devices for controlled and mode-dependent heating of a memory device are described. In various examples, a memory device or an apparatus that includes a memory device may have circuitry configured to heat the memory device. The circuitry configured to heat the memory device may be activated, deactivated, or otherwise operated based on an indication of a temperature (e.g., of the memory device). In some examples, activating or otherwise operating the circuitry configured to heat the memory device may be based on an operating mode (e.g., of the memory device), which may be associated with certain access operations or operational states (e.g., of the memory device). Various operations or operating modes (e.g., of the memory device) may also be based on indications of a temperature (e.g., of the memory device).

The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.