Methods, systems, and devices for feedback for multi-level signaling in a memory device are described. A receiver may use a modulation scheme to communicate information with a host device. The receiver may include a first circuit, a second circuit, a third circuit, and a fourth circuit. Each of the first circuit, the second circuit, the third circuit, and the fourth circuit may determine, for a respective clock phase, a voltage level of a signal modulated using the modulation scheme. The receiver may include a first feedback circuit, a second feedback circuit, a third feedback circuit, and a fourth feedback circuit. The first feedback circuit that may use information received from the first circuit at the first clock phase and modify the signal input into the second circuit for the second clock phase.

The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

A memory cell arrangement is provided that may include: one or more memory cells, each memory cell of the one or more memory cells including: a field-effect transistor structure; a plurality of first control nodes; a plurality of first capacitor structures, a second control node; and a second capacitor structure including a first electrode connected to the second control node and a second electrode connected to a gate region of the field-effect transistor. Each of the plurality of first capacitor structures includes a first electrode connected to a corresponding first control node of the plurality of first control nodes, a second electrode connected to the gate region of the field-effect transistor structure, and a spontaneous-polarizable region disposed between the first electrode and the second electrode of the first capacitor structure.

A CIM bit cell circuit employing a capacitive storage circuit to store a binary weight data as a voltage occupies half or less of the area of a 6T SRAM CIM bit cell circuit, reducing the increase in area incurred in the addition of a CIM bit cell array circuit to an IC. The CIM bit cell circuit includes a capacitive storage circuit that stores binary weight data in a capacitor and generates a product voltage indicating a binary product resulting from a logical AND-based operation of the stored binary weight data and an activation signal. The capacitive storage circuit may include a capacitor and a read access switch or a transistor. The CIM bit cell circuit includes a write access switch to couple a write bit voltage to the capacitive storage circuit. In a CIM bit cell array circuit, the product voltages are summed in a MAC operation.

A CIM bit cell circuit employing a capacitive storage circuit to store a binary weight data as a voltage occupies half or less of the area of a 6T SRAM CIM bit cell circuit, reducing the increase in area incurred in the addition of a CIM bit cell array circuit to an IC. The CIM bit cell circuit includes a capacitive storage circuit that stores binary weight data in a capacitor and generates a product voltage indicating a binary product resulting from a logical AND-based operation of the stored binary weight data and an activation signal. The capacitive storage circuit may include a capacitor and a read access switch or a transistor. The CIM bit cell circuit includes a write access switch to couple a write bit voltage to the capacitive storage circuit. In a CIM bit cell array circuit, the product voltages are summed in a MAC operation.

A memory device may include at least one multinary memory cell. Each multinary memory cell includes a parallel connection of N sub-bit units. N is an integer greater than 1. Each of the N sub-bit units includes a series connection of a respective transistor and a respective capacitor. A first sub-bit unit includes a first capacitor having a capacitance of C, and each i-th sub-unit includes an i-th capacitor having a capacitance of about 2.sup.i-1×C. A multinary bit having 2.sup.N values may be stored. A device network including multiple multinary logic units is also provided. Each of multiple multinary logic unit includes a parallel connection of N sub-bit units. Each sub-bit unit includes a series connection of a respective transistor and a respective capacitor having capacitance ratios of powers of 2.

A system and method for bidirectionally based electrical information storage, processing and communication. Bidirectional memory (tristate) offers the capability to store and interpret multiple bits (Shannon's) of information per memory cell, for structures such as dynamic random-access memory (DRAM), and read-only memory (ROM), and communication circuits, for operation, rather than traditional memory able to store a single “bit” (Shannon) of information per cell. Where, instead of traditional memory cells capable of two possible states (binary digit) and a single defined bit (1 Shannon), bidirectional memory is capable of three states (tristate), where the third information representing state can be a specifically defined state capable of representing multiple bits (multiple Shannon's) for each individual cell, which may be defined to represent a specific sequence of bits (sequence of Shannon's). Additionally, the 3.sup.rd information state of a tristate bidirectional memory cell may be expressed as in a state of constant variability (superposition), where the final determined state may be based on a probabilistic outcome, or probability controlled. The disclosed system and method allows for more complex systems for information storage, compression, processing, communication, and more secure encryption of stored or communicated information.

Methods, systems, and devices for controlled and mode-dependent heating of a memory device are described. In various examples, a memory device or an apparatus that includes a memory device may have circuitry configured to heat the memory device. The circuitry configured to heat the memory device may be activated, deactivated, or otherwise operated based on an indication of a temperature (e.g., of the memory device). In some examples, activating or otherwise operating the circuitry configured to heat the memory device may be based on an operating mode (e.g., of the memory device), which may be associated with certain access operations or operational states (e.g., of the memory device). Various operations or operating modes (e.g., of the memory device) may also be based on indications of a temperature (e.g., of the memory device).

Methods and devices for dynamic allocation of a capacitive component in a memory device are described. A memory device may include one or more voltage rails for distributing supply voltages to a memory die. A memory device may include a capacitive component that may be dynamically coupled to a voltage rail based on an identification of an operating condition on the memory die, such as a voltage droop on the voltage rail. The capacitive component may be dynamically coupled with the voltage rail to maintain the supply voltage on the voltage rail during periods of high demand. The capacitive component may be dynamically switched between voltage rails during operation of the memory device based on operating conditions associated with the voltage rails.

A semiconductor device with a large storage capacity per unit area is provided. The disclosed semiconductor device includes a plurality of gain-cell memory cells each stacked over a substrate. Axes of channel length directions of write transistors of memory cells correspond to each other, and are substantially perpendicular to the top surface of the substrate. The semiconductor device can retain multi-level data. The channel of read transistors is columnar silicon (embedded in a hole penetrating gates of the read transistors). The channel of write transistors is columnar metal oxide (embedded in a hole penetrating the gates of the read transistors and gates, or write word lines, of the write transistors). The columnar silicon faces the gate of the read transistor with an insulating film therebetween. The columnar metal oxide faces the write word line with an insulating film, which is obtained by oxidizing the write word line, therebetween, and is electrically connected to the gate of the read transistor.