A memory device includes a plurality of memory cells arranged in a plurality of rows and a plurality of strings. A method of programming the memory device includes programming a first row of the memory cells. The method also includes, after programing the first row of the memory cells, programming a second row of the memory cells. The second row is adjacent to the first row in a first string direction. The method further includes, after programming the second row of the memory cells, programming a third row of the memory cells. The third row is two rows apart from the second row in a second string direction opposite to the first string direction.

A block family associated with a memory device is created. The block family is associated with a threshold voltage offset bin. A set of read level voltage offsets is determined such that, applying the set of read level voltage offsets to a base read level threshold voltage associated with the block family, result in a suboptimal error rate not exceeding a maximum allowable error rate. The determined set of read level offsets is associated with the threshold voltage offset bin by updating a block family metadata.

According to an embodiment, a semiconductor device includes a control circuit. The control circuit is configured to receive a first command and execute, based on the first command, a first operation and a second operation. The second operation is executed after the first operation. The control circuit is further configured to output a first signal from a start of the first operation to a start of the second operation. The first signal indicates that the semiconductor device is in a busy state in which the semiconductor device refrains from accepting, from an external controller, a second command for execution of the first operation and a third command for execution of the second operation.

In a three dimensional non-volatile memory structure that etches part of the top of the memory structure (including a portion of the select gates), data is stored on a majority (or all but one) of the word lines as x bits per memory cell while data is stored on a top edge word line that is closest to the etching with variable bits per memory cell. In one example embodiment that implements vertical NAND strings, memory cells connected to the top edge word line and that are on NAND strings adjacent the etching store data as n bits per memory cell and memory cells connected to the top edge word line and that are on NAND strings not adjacent the etching store data as m bits per memory cell, where m>x>n.

Apparatuses and techniques are described for modifying program and erase parameters in a memory device in which memory cells can be operated in a single bit per cell (SLC) mode or a multiple bits per cell mode. In one approach, the stress on a set of memory cells in an SLC mode is reduced during programming and erasing when the number of program-erase cycles for the block in the SLC mode is below a threshold. For example, during programming, the program-verify voltage and program voltages can be reduced to provide a shallower than normal programming. During erasing, the erase-verify voltage can be increased while the erase voltages can be reduced to provide a shallower than normal erase. When the number of program-erase cycles for the block in the SLC mode is above the threshold, the program and erase parameters revert to a default levels.

According to one embodiment, a memory system includes a semiconductor memory device and a controller. The device includes a plurality of memory cells capable of storing at least first to third data and a word line coupled to the plurality of memory cells. The first data is determined by a first read operation including a first read level. The second data is determined by a second read operation including a second read level. The third data is determined by a third read operation including a third read level. The controller controls the semiconductor memory device to perform a forth read operation including the first and second read levels in a search operation for first to third read voltages corresponding to the first to third read levels, respectively.

A memory device can dynamically select a voltage step size for programming (i.e., charging) memory cells. The memory device can increase the voltage step size to reduce programming time or decrease the voltage step size to reduce errors. The memory device can identify device conditions, such as temperature or amount of use (e.g., a count of program/erase cycles). The memory device can increase the voltage step size when the device conditions are less likely to cause errors (e.g., in a middle temperature range or below a threshold number of program/erase cycles) or can decrease the voltage step size when the device conditions are more likely to cause errors (e.g., in a high or low temperature range or above a threshold number of program/erase cycles).

A peripheral circuit of a memory device includes page buffers. Each page buffer includes a main latch, a bias latch, (N−1) data latches, and a cache latch coupled to a data path. The peripheral circuit is further configured to: in the process of programming a first physical page, disable a bit line bias function to release the bias latch to replace one of N page latches to perform a programming verification of memory states; release one of the N page latches to cache program data of one of the N logical pages of a second physical page; and in the process of programming the first physical page, store the program data of the one of the N logical pages of the second physical page in a released page latch.

According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.

According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.