Countermeasure method for programming a non-defective plane of a non-volatile memory experiencing a neighbor plane disturb, comprising, once a first plane is determined to have completed programming of a current state but where not all planes have completed the programming, a loop count is incremented and a determination is made as to whether the loop count exceeds a threshold. If so, programming of the incomplete plane(s) is ceased and programming of the completed plane(s) is resumed by suspending the loop count and bit scan mode, and, on a next program pulse, applying a pre-determined rollback voltage to decrement a program voltage bias. The loop count and bit scan mode are resumed once a threshold voltage level equals a program voltage bias when the loop count was last incremented. BSPF criterion is applied for each programmed state. Advancement to the next loop only occurs if a programmed state is determined incomplete.

A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NAND architecture. Multi-bit weight values are stored encoded as sets of threshold voltages for sets of memory cells. A weight value is stored in multiple memory cells on the same word line and connected between a bit line and a source line, each of the memory cells programmed to one of multiple threshold voltages. When multiplying an input value with the weight value, the word line is biased so that, for at least one of the threshold voltages, the memory cell will be in the linear operation region. Input values are encoded as a set of one or more voltage levels applied to a corresponding set of bit lines, each bit line connected memory cells also storing the weight value, connected to the word line, and connected to the source line.

Devices, systems and methods for improving the performance of a memory device are described. An example method includes performing, based on a plurality of read voltages, read operations on each of a plurality of pages of a memory device, determining, based on the read operations for each page of the plurality of pages, a ones count in each page and a checksum of an error correcting code for each page, generating a first estimator for the checksum and a second estimator for the ones count based on a polynomial regression, determining, based on the first estimator and the second estimator, an updated plurality of read voltages, and applying the updated plurality of read voltages to the memory device to retrieve information from the memory device.

A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and arranged in strings and configured to retain a threshold voltage corresponding to memory states. A control circuit is configured to program the memory cells to reach one of a plurality of verify levels each corresponding the memory states using a series of voltage pulses applied to the word lines during a program operation. The control circuit determines an intermediate quantity of the series of voltage pulses necessary for the memory cells associated with a selected one of the memory states to reach the one of the plurality of verify levels corresponding to the selected one of the memory states. The control circuit ends the program operation after a maximum allowable quantity of the series of voltage pulses are utilized. The maximum allowable quantity is selected based on the intermediate quantity.

A method of verifying the programming of a plurality of memory cells in a data storage system includes performing a setup operation including settling of bit lines associated with the subset of memory cells; performing a sensing operation including subjecting the settled bit lines to a verify voltage signal; and performing first and second latching operations identifying memory cells of the subset of memory cells having threshold voltages that meet first and second verify reference voltages, where the first and second latching operations are part of the same program verify operation with no setup time between them.

According to one embodiment, a semiconductor memory device includes a memory cell, a word line, a bit line, a first transistor, a second transistor and a driver. The word line is electrically coupled to a gate of the memory cell. The bit line is electrically coupled to one end of the memory cell. The first transistor includes a first gate electrically coupled to the bit line. The second transistor is coupled to a first end of the first transistor. The driver is configured to apply a voltage to the first gate of the first transistor. In a read operation, the driver varies a voltage to be applied to the first gate of the first transistor based on a read voltage applied to the word line.

In certain aspects, a memory device includes an array of memory cells in columns and rows, word lines respectively coupled to rows, bit lines respectively coupled to the columns, and a peripheral circuit coupled to the array of memory cells through the bit lines and the word lines and configured to program a select row based on a current data page. Each memory cell is configured to store a piece of N-bits data at one of 2.sup.N levels, where N is an integer greater than 1. The peripheral circuit includes page buffer circuits respectively coupled to the bit lines. Each page buffer circuit includes one cache storage unit, one multipurpose storage unit, and N−1 data storage units. The cache storage unit is configured to sequentially receive N bits of the current data page and N bits of a next data page, and sequentially store one of the N bits of the current data page and each of the N bits of the next data page. The multipurpose storage unit is configured to sequentially store non-data page information and one of the N bits of the next data page. The data storage units each is configured to store a respective one of the N bits of the current data page.

The present disclosure provides a three-dimensional NAND memory device, comprising a first NAND string including a first channel corresponding to a first cell to be inhibited to program, and a controller configured to control a word line driver and a bit line driver to do the following operations: prior to applying a program voltage to a selected word line, charging a first bit line electrically coupling with the first channel to a first voltage level for charging the first channel to the first voltage level, charging an array common source electrically coupling with the first bit line for further charging the first channel to a second voltage level higher than the first voltage level, and cutting off the electrical coupling between the first bit line and the first channel for preparing to apply the program voltage to the selected word line.

Apparatuses and techniques are described for detecting latent defects in a memory device by considering both physical segment and logical segment fail bits in an erase operation. The erase operation involves performing a series of erase loops until the memory cells pass an erase-verify test. The passing of the erase-verify test is based on counting memory cells in different logical segments which fail the verify test and determining that the count is less than a logical segment threshold for each logical segment. Subsequently, the technique involves counting memory cells in each physical segment which fail the erase-verify test and determining whether the count is less than a physical segment threshold. If the count is equal to or greater than the physical segment threshold for one or more of the physical segments, the block of memory cells is marked as being bad.

Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.