Systems and methods are provided for employing analog content addressable memory (aCAMs) to achieve low latency complex distribution sampling. For example, an aCAM core circuit can include an aCAM array. Amplitudes of a probability distribution function are mapped to a width of one or more aCAM cells in each row of the aCAM array. The aCAM core circuit can also include a resistive random access memory (RRAM) storing lookup information, such as information used for processing a model. By randomly selecting columns to search of the aCAM array, the mapped probability distribution function is sampled in a manner that has low latency. The aCAM core circuit can accelerate the sampling step in methods relying on sampling from arbitrary probability distributions, such as particle filter techniques. A hardware architecture for an aCAM Particle Filter that utilizes the aCAM core circuit as a central structure is also described.

A nonvolatile memory device comprises: resistive memory cells each of which takes either a variable state or an initial state, the resistive memory cells including at least one resistive memory cell in the initial state; and a read circuit that comprising a resistance detection circuit that obtains resistance value information of the at least one resistive memory cell, and a data generation circuit that generates digital data corresponding to the resistance value information. The resistance detection circuit applies a second read voltage to the at least one resistive memory cell to obtain the resistance value information. The second read voltage is larger than a first read voltage and smaller than a voltage of a forming pulse that is an electrical stress for changing from the initial state to the variable state. The first read voltage is for reading a resistive memory cell in the variable state.

A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.

Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described. In one embodiment, a cross-point memory cell includes a word line extending in a first direction, a bit line extending in a second direction different from the first direction, the bit line and the word line crossing without physically contacting each other, and a capacitor formed between the word line and the bit line where such cross. The capacitor comprises a dielectric material configured to prevent DC current from flowing from the word line to the bit line and from the bit line to the word line.

A memory chip, a memory system, and a method of accessing the memory chip. The memory chip includes a substrate, a first storage unit, and a second storage unit. The first storage unit includes a plurality of first memory cells may have a first storage capacity of 2.sup.n. The plurality of first memory cells may be configured to activate in response to a first selection signal. The second storage unit includes a plurality of second memory cells and may have a second storage capacity of 2.sup.n+1. The plurality of second memory cells may be configured to activate in response to a second selection signal.

To suppress the degradation of memory cells in a non-volatile memory. A read processing unit performs a read process for reading read data from each of a plurality of memory cells on the basis of a first threshold. An error detection unit detects presence or absence of an error in the read data and specifies memory cells in which the error is present among the plurality of memory cells. A re-read processing unit performs a re-read process for reading data, as re-read data, from the specified memory cells on the basis of a second threshold different from the first threshold. A refresh processing unit rewrites, for a memory cell of which the re-read data has a different value from the read data among the specified memory cells, data with the re-read data as a refresh process.

Devices and methods for accessing resistive change elements in a resistive change element array to determine resistive states of the resistive change elements are disclosed. According to some aspects of the present disclosure the devices and methods access resistive change elements in a resistive change element array through a variety of operations. According to some aspects of the present disclosure the devices and methods supply an amount of current tailored for a particular operation. According to some aspects of the present disclosure the devices and methods compensate for circuit conditions of a resistive change element array by adjusting an amount of current tailored for a particular operation to compensate for circuit conditions of the resistive change element array.

An embodiment of a semiconductor apparatus may include technology to convert an analog voltage level of a memory cell of a multi-level memory to a multi-bit digital value, and determine a single-bit value of the memory cell based on the multi-bit digital value. Some embodiments may also include technology to track a temporal history of accesses to the memory cell for a duration in excess of ten seconds, and determine the single-bit value of the memory cell based on the multi-bit digital value and the temporal history. Other embodiments are disclosed and claimed.

A resistive memory structure comprises at least one resistive memory element configured to store one or more bits of data and a circuit electrically connected to the resistive memory element for use in performing at least one of a read or write operation on the at least one resistive memory element. The circuit includes a resistor electrically connected in series to the resistive memory element thereby forming a voltage divider and electrical node therebetween, and an interpretation circuit electrically connected to the electrical node formed between the resistive memory element and the resistor. The interpretation circuit is configured to interpret a voltage at the electrical node and to determine a resistive state of the resistive memory element based on the voltage at the electrical node.

Two-terminal memory can be set to a first state (e.g., conductive state) in response to a program pulse, or set a second state (e.g., resistive state) in response to an erase pulse. These pulses generally provide a voltage difference between the two terminals of the memory cell. Certain electrical characteristics associated with the pulses can be manipulated in order to enhance the efficacy of the pulse. For example, the pulse can be enhanced or improved to reduce power-consumption associated with the pulse, reduce a number of pulses used to successfully set the state of the memory cell, reduce wear or damage to the memory cell, or to improve Ion or Ioff distribution associated with changing the state of the memory cell.