The present disclosure relates to a method of programming resistive memory cells of a resistive memory, the method comprising: applying, by a programming circuit based on a first target resistive state, an initial resistance modification to a first cell of the resistive memory to change its resistance from an initial resistive state to a first new resistance; comparing, by the programming circuit, the first new resistance of the first cell with a resistance range of the first target resistive state and with a target resistance range associated with the first target resistive state; and if it is determined that the first new resistance is outside the resistance range of the target resistive state and inside the target resistance range, applying by the programming circuit one or more further resistance modifications to the first cell to increase or decrease its resistance.

This application relates to computing circuitry (200, 500, 600) for analogue computing. A plurality of current generators (201) are each configured to generate a defined current (I.sub.D1, I.sub.D2, . . . I.sub.Dj) based on a respective input data value (D.sub.1, D.sub.2, . . . D.sub.j). A memory array (202), having at least one set (204) of programmable-resistance memory cells (203), is arranged to receive the defined currents from each of the current generators at a respective signal line (206). Each set (204) of programmable-resistance memory cells (203) includes a memory cell associated with each signal line that, in use, can be connected between the relevant signal line and a reference voltage so as to generate a voltage on the signal line. An adder module (207) is coupled to each of the signal lines to generate a voltage at an output node (210) based on the sum of the voltages on each of the signal lines.

Aspects of the subject disclosure may include, for example, applying a setting voltage across first and second electrodes, wherein a nanowire with a first electrical resistance is electrically connected between the first and second electrodes, wherein the applying of the setting voltage causes a migration of ions from the first and/or second electrodes to a surface of the nanowire, and wherein the migration of ions effectuates a reduction of electrical resistance of the nanowire from the first electrical resistance to a second electrical resistance that is lower than the first electrical resistance; and applying a reading voltage across the pair of electrodes, wherein the reading voltage is less than the setting voltage, and wherein the reading voltage is sufficiently small such that the applying of the reading voltage causes no more than an insignificant change of the electrical resistance of the nanowire from the second electrical resistance. Other embodiments are disclosed.

A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.

This application relates to methods and apparatus for computing, especially to circuitry for performing computing, at least partly, in the analogue domain. The circuitry (200) comprises a plurality of memory cells (201), each memory cell having first and second paths between an electrode (202) for receiving an input current and respective positive and negative electrodes (203) for outputting a differential-current output. Memristors (101) are located in the first and second paths. The memory cells are configured into sets (205) of memory cells, the memory cells of each said set being connected so as to provide a differential current set output that corresponds to a combination of the cell outputs of all of the memory cells of that set. For each set, at least some of the memory cells of that set are configured to receive a different input current to other memory cells of that set.

A programmable resistive memory element and a method of adjusting a resistance of a programmable resistive memory element are provided. The programmable resistive memory element includes at least one resistive memory element. Each resistive memory element includes an Indium-Gallium-Zinc-Oxide (IGZO) resistive layer, a first electrical contact and a second electrical contact. The first and second electrical contacts are disposed on the IGZO resistive layer in the same plane. The programmable resistive memory element includes a voltage generator coupled to the first and second electrical contacts, constructed and arranged to apply a thermal treatment to the resistive memory element to adjust a resistance of the resistive memory element.

A semiconductor device may include a word line, a bit line crossing the word line, and a memory cell coupled to the word line and the bit line to receive an electrical signal to control the memory cell and including a switching material layer and an oxidation-reduction reversible material layer that is in contact with the switching material layer to allow for either oxidation reaction or reduction reaction to occur in response to different amplitudes and different polarities of the electrical signal, wherein the oxidation-reduction reversible material layer and the switching material layer responds to a first threshold voltage and a first polarity of the electrical signal to generate an oxidation interface between the switching material layer and the oxidation-reduction reversible material layer, and responds to a second threshold voltage and a second polarity of the electrical signal to reduce the generation of the oxidation interface.

Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

There are provided a variable resistance memory device and a manufacturing method of the same. The variable resistance memory device includes: a first electrode; a second electrode arranged in a vertical direction from the first electrode; and an oxide layer having an oxygen deficient region extending in the vertical direction between the second electrode and the first electrode.

An embodiment of the invention may include a memory structure. The memory structure may include a first terminal connected to a first contact. The memory structure may include a second terminal connected to a second contact and a third contact. The memory structure may include a multi-level nonvolatile electrochemical cell having a variable resistance channel and a programming gate. The memory structure may include the first contact and second contact connected to the variable resistance channel. The memory structure may include the third contact is connected to the programming gate. This may enable decoupled read-write operations of the device.