A device may include a first die having a first circuit and a second die having a second circuit. The die may be separated by a material layer. The material layer may include multiple through-silicon vias (TSVs) for electrically coupling the first die to the second die. A first TSV of the TSVs may electrically couple the first circuit to the second circuit and a second TSV of the TSVs may include a redundant TSV that electrically bypasses the first TSV to couple the first circuit to the second circuit if a fault is detected in the first TSV.

The present disclosure is directed to a method for storing information in a coded manner in non-volatile memory cells. The method includes providing a group of non-volatile memory cells of non volatile memory. The memory cell is of the type in which a stored logic state, which can be logic high or logic low, can be changed through application of a current to the cell and the state in the memory cell is read by reading a current provided by the cell. The group of non-volatile memory cells include a determined number of non-volatile memory cells which is greater than two. The group of non-volatile memory cells store a codeword formed by the values of said stored states of the cells of the group taken according to a given order. Given a set of codewords obtainable by the stored values in the determined number of non-volatile memory cells in a group, the method includes storing the information in at least two subsets of said set of codewords comprising each at least a codeword. Each codeword in a same subset has a same Hamming weight. Each codeword belonging to one subset has a Hamming distance equal or greater than two with respect to each codeword belonging to another subset.

Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.

Disclosed herein are related to a system and a method of extending a lifetime of a memory cell. In one aspect, a memory controller applies a first pulse having a first amplitude to the memory cell to write input data to the memory cell. In one aspect, the memory controller applies a second pulse having a second amplitude larger than the first amplitude to the memory cell to extend a lifetime of the memory cell. The memory cell may include a resistive memory device or a phase change random access memory device. In one aspect, the memory controller applies the second pulse to the memory cell to repair the memory cell in response to determining that the memory cell has failed. In one aspect, the memory controller periodically applies the second pulse to the memory cell to extend the lifetime of the memory cell before the memory cell fails.

A nonvolatile memory apparatus may include a control circuit, a sense amplifier, and a reference generator. The control circuit may apply a read voltage across a target memory cell through a selected global bit line and a selected global word line. The sense amplifier may generate an output signal by comparing voltage levels of the selected global word line and a reference line. The reference generator may change the voltage level of the reference line by charging and discharging a capacitor that is coupled to the reference line.

A control method to operate a memory device, a control method to operate a memory system and a control system are provided. The control method includes providing a first voltage to a memory device for accessing a memory element of the memory device; obtaining an aging information of the memory device; and providing a second voltage to the memory device according to the aging information, wherein the first voltage and the second voltage are reverse biased voltages.

The generation of “fingerprints”, also called challenge-response pairs (CRPs) of Physically Unclonable Functions (PUFs), can often stress electronic components, leaving behind traces that can be exploited by crypto-analysts. A non-intrusive method to generate CRPs based on Resistive RAMs may instead be used, which does not disturb the memory cells. The injection of small electric currents (magnitude of nanoAmperes) in each cell causes the resistance of each cell to drop abruptly by several orders of magnitudes through the formation of temporary conductive paths in each cell. A repeated injection of currents into the same cell, results in an almost identical effect in resistance drop for a single cell. However, due to the small physical variations which occur during manufacturing, the cells are significantly different from each other, in such a way that a group of cells can be used as a basis for PUF authentication.

Embodiments of three-dimensional (3D) memory devices with embedded dynamic random-access memory (DRAM) and methods for forming the 3D memory devices are disclosed. In an example, a method for operating a 3D memory device is disclosed. The 3D memory device includes an input/output circuit, an array of embedded DRAM cells, and an array of 3D NAND memory strings in a same chip. Data is transferred through the input/output circuit to the array of embedded DRAM cells. The data is buffered in the array of embedded DRAM cells. The data is stored in the array of 3D NAND memory strings from the array of embedded DRAM cells.

Three-dimensional (3D) memory devices with 3D phase-change memory (PCM) and methods for forming and operating the 3D memory devices are disclosed. In an example, a 3D memory device includes a first semiconductor structure including an array of NAND memory cells, and a first bonding layer including first bonding contacts. The 3D memory device also further includes a second semiconductor structure including a second bonding layer including second bonding contacts, a semiconductor layer and a peripheral circuit and an array of PCM cells between the second bonding layer and the semiconductor layer. The 3D memory device further includes a bonding interface between the first and second bonding layers. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

A nonvolatile memory apparatus performs a plurality of read operations by using a plurality of read voltages. A first read operation is performed by applying a first read voltage to a memory cell. A second read operation is selectively performed based on whether a snap-back of the memory cell occurs during the first read operation. The second read operation is performed by applying a second read voltage having a higher voltage level than the first read voltage to the memory cell.