The present disclosure relates to resistive random-access memory (RRAM) devices. In some embodiments, a RRAM device may include a first electrode, a second electrode, and a switching oxide layer positioned between the first electrode and the second electrode, wherein the switching oxide layer comprises at least one transition metal oxide. The second electrode may include a first layer comprising a first metallic material and a second layer comprising a second metallic material. In some embodiments, the first metallic material and the second metallic material may include titanium and tantalum, respectively. In some embodiments, the second electrode may include an alloy of tantalum. The alloy of tantalum may contain one or more of hafnium, molybdenum, niobium, tungsten, and/or zirconium. In some embodiments, the alloy of tantalum contains a plurality of alloys of tantalum.

The present disclosure relates to resistive random-access memory (RRAM) devices. In some embodiments, a RRAM device may include a first electrode; a second electrode comprising an alloy containing tantalum; and a switching oxide layer positioned between the first electrode and the second electrode, wherein the switching oxide layer includes at least one transition metal oxide. The alloy containing tantalum may further contain at least one of hafnium, molybdenum, tungsten, niobium, or zirconium. In some embodiments, the alloy containing tantalum may include one or more of a binary alloy containing tantalum, a ternary alloy containing tantalum, a quaternary alloy containing tantalum, a quinary alloy containing tantalum, a senary alloy containing tantalum, and a high order alloy containing tantalum.

The present disclosure relates to resistive random-access memory (RRAM) devices. In some embodiments, an RRAM device includes: a first electrode including a metal nitride; a second electrode comprising a first conductive material; and a switching oxide layer positioned between the first electrode and the second electrode. The switching oxide layer includes at least one transition metal oxide. In some embodiments, the metal nitride in the first electrode includes titanium nitride and/or tantalum nitride. The first electrode does not include a non-reactive metal, such as platinum (Pt), palladium (Pd), etc.

An apparatus for performing in-memory processing includes a memory cell array of memory cells configured to output a current sum of a column current flowing in respective column lines of the memory cell array based on an input signal applied to row lines of the memory cells, a sampling circuit, comprising a capacitor connected to each of the column lines, configured to be charged by a sampling voltage of a corresponding current sum of the column lines, and a processing circuit configured to compare a reference voltage and a currently charged voltage in the capacitor in response to a trigger pulse generated at a timing corresponding to a quantization level, among quantization levels, time-sectioned based on a charge time of the capacitor, and determine the quantization level corresponding to the sampling voltage by performing time-digital conversion when the currently charged voltage reaches the reference voltage.

A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.

A vertical resistive memory array is presented. The array includes a pillar electrode and a switching liner around the side perimeter of the pillar electrode. The array includes two or more vertically stacked single cell (SC) electrodes connected to a first side of the switching liner. The juxtaposition of the switching liner, the pillar electrode, and each SC electrode forms respective resistance switching cells (e.g., OxRRAM cell). A vertical group or bank of these cells may be connected in parallel and each share the same pillar electrode. The cells in the vertical cell bank may written to or read from as a group to limit the effects of inconsistent CF formation of any one or more individual cells within the group.

A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.

An integrated circuit (IC) device includes a substrate, and a memory array layer having a plurality of transistors. First through fourth gate contacts are arranged along a first axis, and coupled to underlying gates of the plurality of transistors. First through fifth source/drain contacts in the memory array layer extend along a second axis transverse to the first axis, and are coupled to underlying source/drains of the plurality of transistors. The gate contacts and the source/drain contacts are alternatingly arranged along the first axis. A source line extends along the first axis, and is coupled to the first and fifth source/drain contacts. First and second word lines extend along the first axis, the first word line is coupled to the first and third gate contacts, and the second word line is coupled to the second and fourth gate contacts.

An apparatus for generating a binary numerical sequence is provided. The apparatus is configured to apply a first write voltage or a second write voltage, different from the first write voltage, as a write voltage to each of two or more switchable elements, and/or to apply a first read voltage or a second read voltage, different from the first read voltage, as a read voltage to each of the two or more switchable elements. Each switchable element of the two or more switchable elements is configured to output, in dependence on the write voltage applied to the switchable element and/or in dependence on the read voltage applied to the switchable element, an output voltage with a first random or pseudo-random voltage value from a first voltage value range or with a second random or pseudo-random voltage value from a second voltage value range.

A resistive element array circuit includes word lines, bit lines, resistive elements, a selector, a differential amplifier, and a ground terminal. The word lines are coupled to a power supply. The resistive elements are each disposed at an intersection of corresponding one of the word lines and corresponding one of the bit lines. The selector is configured to select one word line and one bit line. The differential amplifier includes a positive input terminal configured to be coupled to the selected one of the bit lines which is selected by the selector, a negative input terminal configured to be coupled to non-selected one of the bit lines which is not selected by the selector and to non-selected one of the word lines which is not selected by the selector, an output terminal being coupled to the negative input terminal. The ground terminal is coupled to the positive input terminal.