A sensor system includes a sensor configured to measure a parameter. The sensor system also includes a memory configured to record one or more occurrences when the parameter is outside of a predetermined range. The memory includes a wire, a counter-electrode, and an electrolyte.

Some embodiments include a memory cell having a non-ohmic device between a transistor source/drain region and a capacitor. Some embodiments include a memory cell having a transistor with a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. A capacitor is electrically coupled to the second source/drain region through a non-ohmic device. The non-ohmic device includes a non-ohmic-device-material which changes conductivity in response to an electrical property along the channel region. The non-ohmic-device-material has a high-resistivity-mode when the electrical property along the channel region is below a threshold level, and transitions to a low-resistivity-mode when the electrical property along the channel region meets or exceeds the threshold level. Some embodiments include a memory array.

An electrochemical device includes an electrochemical cell and an electric circuit. The electrochemical cell comprises a first solid component and a second solid component. The two solid components comprise same chemical elements but have different concentrations of at least one type of the chemical elements. A solid electrolyte is arranged between the two solid components. The solid electrolyte is a dielectric material. The electric circuit is connected to the electrochemical cell. The electrochemical cell may be operated according to a redox process, so as to exchange chemical elements of the at least one type between the first solid component and the second solid component and thereby change an electrical conductance of each of the two solid components.

A resistive switching memory device according to an exemplary embodiment includes: a first electrode; a second electrode formed to be separated from the first electrode; and an insulating layer formed near the first electrode and the second electrode, and changed to one of a high resistance state and a low resistance state when a conductive filament is controlled by a change of external humidity or a voltage applied through the first electrode or the second electrode.

An electro-chemical random-access memory (ECRAM) cell includes a substrate and a plurality of source-drain pairs positioned on a top surface of the substrate, each source-drain pair comprising a source and a drain. A channel at least partially overlays the substrate and the plurality of source-drain pairs, and a transfer layer at least partially overlays the channel. A gate at least partially overlays the transfer layer, the gate at least partially controlling a channel between each source-drain pair.

A memory device and an operation method thereof for performing a multiply-accumulate operation are provided. The memory device includes at least one memory string, a plurality of data lines and a string line. The memory string includes a plurality of unit cells having a plurality of stored values. The data lines are respectively connected to the unit cells to receive a plurality of data signals having a plurality of inputting values. When the data signals are inputted into the unit cells, a plurality of nodes among the unit cells are kept at identical voltages. The string line is connected to the memory string to receive a sensing signal and obtain a measured value representing a sum-of-product result of the inputting values and the stored values. The data signals and the sensing signal are received at different time.

A content addressable memory (CAM) structure is provided. The CAM comprises a plurality of CAM cells communicatively coupled to processing circuitry. A plurality of threshold switching (TS) memristors are included, each configured to connect to a one of the plurality of CAM cells, with the first end connected to the CAM cell and the second connected to a match line. A discharge transistor is included and configured to discharge any charge on the match line in response to the CAM receiving a command to perform a search.

An optoelectronic memristor includes a first electrode, a second electrode, and a solid electrolyte in between that is in electrical communication with the first electrode and the second electrode. The solid electrolyte has an electronic conductivity of about 10.sup.10 Siemens/cm to about 10.sup.4 Siemens/cm at room temperature. The first electrode, and optionally the second electrode, can be optically transparent at a specific wavelength and/or a wavelength range. A direct current (DC) voltage source is employed to apply an electric field across the solid electrolyte, which induces a spatial redistribution of ionic defects in the solid electrolyte. In turn, this causes a change in electrical resistance of the solid electrolyte. The application of the electric field can also cause a change in an optical property of the solid electrolyte at the specific wavelength, and/or at the wavelength range (or a portion thereof).

A content addressable memory (CAM) structure is provided. The CAM comprises a plurality of CAM cells communicatively coupled to processing circuitry. A plurality of threshold switching (TS) memristors are included, each configured to connect to a one of the plurality of CAM cells, with the first end connected to the CAM cell and the second connected to a match line. A discharge transistor is included and configured to discharge any charge on the match line in response to the CAM receiving a command to perform a search.

A method is presented for mitigating conductance drift in intercalation cells for neuromorphic computing. The method includes forming a first electro-chemical random access memory (ECRAM) structure over a substrate and forming a second ECRAM over the substrate, the first and second ECRAMs sharing a common contact. The common contact can be either a source contact or a drain contact. Each of the first and second ECRAMs can include a tungsten oxide layer, an electrolyte layer, and a gate contact.