A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.

Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate transfer of stored values between the volatile and non-volatile memory bitcells.

A circuit cell for a memory device or a logic device comprises: (i) first and a second logic gates having respective output nodes; and (ii) first and second memory units, each comprising (a) first and second terminals and (b) a resistive memory element and a bipolar selector connected in series between the first and second terminals, wherein the first terminals of the first and second memory units are connected to the output nodes of the first and second logic gates, respectively, wherein the resistive memory elements are configured to be switchable between first and second resistance states, and wherein in response to a switching current and the bipolar selectors are configured to be conducting in response to an absolute value of a voltage difference across the bipolar selectors exceeding a threshold voltage of the bipolar selectors and non-conducting in response to the absolute value being lower than the threshold.

A semiconductor circuit of the present disclosure includes: a first circuit that is configured to apply an inverted voltage of a voltage at a first node to a second node; a second circuit that is configured to apply an inverted voltage of a voltage at the second node to the first node; a first transistor that is configured to couple the first node to a third node to which a first memory element is coupled; a second transistor having a drain coupled to the third node and a gate coupled to a first predetermined node; a third transistor having a drain coupled to the third node and a gate coupled to a second predetermined node; a fourth transistor that is configured to couple the second node to a fourth node to which a second memory element is coupled; a fifth transistor having a drain coupled to the fourth node and a gate coupled to the second predetermined node; and a sixth transistor having a drain coupled to the fourth node and a gate coupled to the first predetermined node.

Methods and systems are provided that may include a nonvolatile memory to store information, where the nonvolatile memory is associated with a configuration register to indicate a write speed setting for at least one write operation to the nonvolatile memory. A circuit may supply current to achieve an indicated write speed setting for the at least one write operation to the nonvolatile memory.

A mixed mode memory comprises a memory array, a word line decoder, an intermediary circuit and a reading and writing circuit, wherein the word line decoder is electrically coupled to the memory array, and the intermediary circuit is electrically coupled to the memory array and the writing circuit. The memory array comprises mixed mode memory cells with each cell comprising a reading and writing component group, a storage circuit and a selection circuit. The reading and writing component group is electrically coupled to a word line which controls the reading and writing component group to be conducted or not conducted, and electrically coupled to two bit lines which respectively transmit two data signals. The storage circuit generates two reading response signals based on a reading drive signal. The selection circuit controls the storage circuit to operate in a volatile or non-volatile storage mode based on a selection voltage.

A mixed mode memory cell comprises a reading and writing component group, a storage circuit and a selection circuit. The reading and writing component group is electrically coupled to a word line and two bit lines, wherein the two bit lines respectively transmit two data signals. The storage circuit is electrically coupled to the reading and writing component group. The selection circuit is electrically coupled to the reading and writing component group and the storage circuit, and configured to control the storage circuit to operate in a volatile storage mode or a non-volatile storage mode based on a selection voltage.

The disclosed technology relates to a non-volatile (NV) static random-access memory (SRAM) device, and to a method of operating the same. The NV-SRAM device includes a plurality of bit-cells, wherein each bit-cell comprises: an SRAM bit-cell; a first bit-line connected via a first access element to the SRAM bit-cell; a NV bit-cell connected via a switch to the SRAM bit-cell; and a second bit-line connected via a second access element to the NV bit-cell. The NV-SRAM device is configured to independently write data from the first bit-line into the SRAM bit-cell through the first access element, and respectively from the second bit-line into the NV bit-cell through the second access element.

A semiconductor circuit of the present disclosure includes: a first circuit that is configured to apply an inverted voltage of a voltage at a first node to a second node; a second circuit that is configured to apply an inverted voltage of a voltage at the second node to the first node; a first transistor that is configured to couple the first node to a third node to which a first memory element is coupled; a second transistor having a drain coupled to the third node and a gate coupled to a first predetermined node; a third transistor having a drain coupled to the third node and a gate coupled to a second predetermined node; a fourth transistor that is configured to couple the second node to a fourth node to which a second memory element is coupled; a fifth transistor having a drain coupled to the fourth node and a gate coupled to the second predetermined node; and a sixth transistor having a drain coupled to the fourth node and a gate coupled to the first predetermined node.

A semiconductor circuit of the present disclosure includes: a first circuit that is configured to apply an inverted voltage of a voltage at a first node to a second node; a second circuit that is configured to apply an inverted voltage of a voltage at the second node to the first node; a first transistor that is configured to couple the first node to a third node; a first memory element having a first terminal coupled to the third node and a second terminal to which a control voltage is to be applied; a second transistor having a source to which a first voltage is to be applied, a drain coupled to the third node, and a gate coupled to a first predetermined node being one of the first node and the second node; a third transistor having a source to which a second voltage is to be applied, a drain coupled to the third node, and a gate coupled to a second predetermined node being the other of the first node and the second node; and a driver.