A TCAM comprises a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings and one or more current sensing units. The memory cell strings comprise a plurality of memory cells. The current sensing units are coupled to the memory cell strings. In a search operation, a determination that whether any of the data stored in the memory cell strings matches a data string to be searched is made according to whether the one or more current sensing units detect current from the memory cell strings, or according to the magnitude of the current flowing out from the memory cell strings detected by the one or more current sensing units. Each memory cell includes a first transistor and a second transistor. Gates of the first and second transistors are coupled to a corresponding first search line and a corresponding second search line.

The present invention discloses a memory device and operation method thereof. The operation method comprises: programming a plurality of first strings of a plurality of string pairs representing a finite state machine (FSM) to an in-memory-searching (IMS) array of a memory device; programming a plurality of second strings of the string pairs to a working memory of the memory device; and programming a string representing a starting state of the FSM to a buffer of the memory device.

An analog CAM and an operation method thereof are provided. The analog CAM includes a matching line, an analog CAM cell and a sense amplifier. Each of the at least one analog CAM includes a first floating gate device having a N type channel and a second floating gate device having a P type channel. A match range is set through programming the first floating gate device and the second floating gate device. The sense amplifier is connected to the matching line. If an inputting signal is within the match range, a voltage of the matching line is pulled down to be equal to or lower than a predetermined level. The sense amplifier outputs a match result if the voltage of the matching line is pulled down to a predetermined level.

An example ternary content addressable memory. A bit cell of the memory may include first and second memristors, with a first terminal of the first memristor being connected to a first terminal of the second memristor via a node, a second terminal of the first memristor being switchably connected to a first data line, and a second terminal of the second memristor being switchably connected to a second data line. The bit cell may also include a match-line transistor that is connected between a first rail and a match line, with a gate of the match-line transistor being connected to the node.

Disclosed are TCAM device and operation method thereof. The operation method of the TCAM device comprises: applying a select voltage on one of a plurality of first signal lines, and applying an pass voltage on the rest of the first signal lines, wherein the TCAM device comprises an IMS array, the IMS array comprises a plurality of memory units, the memory units are arranged as a plurality of rows and a plurality of columns, a plurality of control terminal of each row of the memory units are coupled to the first driving circuit via a first signal line, each column of the memory units are serially connected to form a memory unit string, each of the memory unit string is coupled to the second driving circuit via a second signal line; and applying a plurality of searching voltage corresponding to a target data to the second signal lines.

Systems and methods are provided for employing analog content addressable memory (aCAMs) to achieve low latency complex distribution sampling. For example, an aCAM core circuit can include an aCAM array. Amplitudes of a probability distribution function are mapped to a width of one or more aCAM cells in each row of the aCAM array. The aCAM core circuit can also include a resistive random access memory (RRAM) storing lookup information, such as information used for processing a model. By randomly selecting columns to search of the aCAM array, the mapped probability distribution function is sampled in a manner that has low latency. The aCAM core circuit can accelerate the sampling step in methods relying on sampling from arbitrary probability distributions, such as particle filter techniques. A hardware architecture for an aCAM Particle Filter that utilizes the aCAM core circuit as a central structure is also described.

Memory devices might include a plurality of memory cell pairs each configured to be programmed to store a digit of data; and control circuitry configured to cause the memory device to compare the stored digit of data of each memory cell pair to a received digit of data, determine whether a match condition or a no-match condition is indicated between the stored digit of data of each memory cell pair and the received digit of data, and deem a match condition to be met between the received digit of data and the stored digits of data of the plurality of memory cell pairs in response to a match condition being determined for a majority of memory cell pairs of the plurality of memory cell pairs.

A method to determine an extreme value of a plurality of data candidates includes storing each data candidate of a plurality of data candidates in a separate column of an associative memory, initializing a row of marker bits by setting each marker bit to a value of 1, computing a subsequent row of marker bits by performing in parallel a Boolean AND operation between a previous row of marker bits and a row of bits of the data candidates, starting with the row of most significant bits of the data candidates, performing a Boolean OR operation between the marker bits in the subsequent row of marker bits to generate a subsequent RSP value, identifying the extreme value from among the plurality of data candidates when there is only one marker bit having a value of 1 in the subsequent row of marker bits coinciding with when said subsequent RSP value is a 1, and if the identifying is false, repeating the computing on a row of next most significant bits, performing and identifying until the identifying is true.

A tunable CMOS circuit comprising a CMOS element and a tunable load. The CMOS element is configured to receive in an analogue input signal. The tunable load is connected to the CMOS element and configured to set a switch point of the CMOS element. The CMOS element is configured to output an output current that is largest when the analogue input signal is equal to the switch point. The combination of a CMOS element with a tunable load may also provide a hardware implementation of fuzzy logic. A fuzzy logic gate comprises an input node, a CMOS logic gate including a tunable load, and an output node. The input node is configured to receive an analogue input signal. The CMOS logic gate is connected to the input node. The tunable load is provided on a current path connected to the output node. The output node is configured to output an analogue output signal.

A voltage generation circuit includes a driver configured to generate an internal voltage by driving an external voltage depending on a driving signal; an amplifier configured to generate the driving signal depending on a result of comparing a reference voltage and a feedback voltage; and a switch configured to delay a decrease of the internal voltage by precharging a node of the amplifier with a predetermined voltage depending on a control signal.